Wafer Probe Testing — electrically testing every die on a wafer before dicing and packaging, identifying defective chips early to avoid wasting expensive packaging resources.

Process

1. Wafer placed on probe station (temperature-controlled chuck) 2. Probe card with hundreds/thousands of tiny needles contacts die pads 3. ATE (Automatic Test Equipment) sends test patterns and measures responses 4. Each die marked pass/fail (ink dot or electronic wafer map) 5. Only passing die proceed to packaging

What Is Tested

• DC Tests: Leakage current, drive strength, threshold voltage
• Functional Tests: Apply scan patterns, check logic correctness
• Speed Tests (Shmoo): Find maximum operating frequency
• Memory BIST: Built-in self-test for all on-chip SRAMs
• Analog Tests: ADC/DAC linearity, PLL lock range

Test Economics

• Packaging cost per die: $1–50+ depending on package type
• Wafer test catches 10–30% defective die before packaging
• ROI: Testing a $0.01 die to avoid $10 packaging cost

Probe Technology

• Cantilever probes: Traditional, flexible
• MEMS probes: Higher density, better for fine-pitch pads
• Vertical probes: For flip-chip bump arrays

Wafer probe is the quality gate between fabrication and packaging — it ensures only functional die proceed through the expensive assembly process.