Wafer Probe Testing and Known-Good-Die (KGD) Methodology is the process of electrically testing every die on a wafer before singulation and packaging, using a probe card to contact bond pads or bumps and execute test programs that measure functional and parametric performance — KGD methodology extends this concept to guarantee bare-die quality for multi-chip module, 2.5D, and 3D stacked applications.

• Probe Card Technology: Cantilever, vertical, and MEMS probe cards hold thousands of probe tips aligned to the die pad array. Advanced probe cards for fine-pitch flip-chip bumps use micro-spring or cobra-style probes with tip diameters below 15 µm. Probe-tip planarity and contact resistance (< 1 Ω) are critical for accurate measurements.
• Test Program Structure: At-speed functional tests apply clock signals at the target frequency and compare outputs against expected patterns stored in tester memory. Parametric tests measure leakage current (Iddq), threshold voltage, ring-oscillator frequency, SRAM read/write margins, and I/O timing to grade die by speed bin.
• Wafer-Level Burn-In (WLBI): Some KGD flows include burn-in at the wafer level, stressing die at elevated voltage and temperature for hours to screen out early-life failures (infant mortality). This is especially important for HBM and chiplet applications where field replacement is impossible.
• Test Coverage and DPM: Test quality is measured by defect-per-million (DPM) escapes. Comprehensive fault models (stuck-at, transition, path-delay, cell-aware) combined with built-in self-test (BIST) for SRAM and logic achieve test coverage above 99%. Low DPM levels require both structural and functional testing.
• Inking and Mapping: Failed die are marked (inked) or digitally mapped in a wafer map file (SINF, XML). Downstream assembly reads this map to pick only good die, avoiding the cost of packaging defective parts.
• Known-Good-Die (KGD): For chiplet-based products, every bare die must be fully qualified before integration. KGD requires testing at-speed and at-temperature to match final-package conditions, plus additional screening for latent defects. The cost of a single bad die in a multi-chiplet package can be hundreds of dollars due to yield loss of the entire assembly.
• Test Economics: Tester time is expensive ($1–5 per die-second on high-end ATE). Design-for-test (DFT) techniques—scan chains, BIST, test compression—reduce test time by 10–100× while maintaining coverage.
• Contactless and Optical Probing: Emerging techniques such as electro-optic probing and photo-emission testing enable noncontact characterization of high-speed signals and failure localization without physical probe contact. Wafer probe testing and KGD methodology together ensure that only electrically verified die proceed to packaging, a discipline that becomes ever more critical as heterogeneous integration architectures place escalating demands on bare-die outgoing quality.