Wafer sort. or wafer probe electrically tests individual dies while they remain on the wafer, before singulation and packaging. A prober positions and temperature-controls the wafer, aligns pads or bumps to a probe card, establishes contact, and indexes die sites. Automated test equipment applies power, DC measurements, clocks, scan or functional patterns, memory algorithms, analog or RF stimuli, and captures responses. The test program assigns bins and writes a wafer map used for assembly selection, repair, process learning, and traceability. Manufacturing economics and outgoing quality emerge from a linked system of design rules, process capability, inspection, electrical test, screening, failure analysis, and learning. A metric is useful only when its population, unit, sampling, censoring, test conditions, revision, and uncertainty are declared. Wafer yield, assembly yield, final-test yield, quality escape rate, reliability fallout, and customer return rate measure different filters. Improving one by rejecting more material can worsen cost without improving the underlying process, so ownership follows failure mechanism rather than a dashboard color.

Models, mechanisms, and interpretation. Probe contact must break or penetrate surface contamination without damaging pads, bumps, passivation, or underlying structures. Contact resistance, scrub, force, planarity, temperature expansion, vibration, and contamination affect measurements. High parallelism shares power, thermal, timing, and instrument resources among sites, so one unstable contact can disturb neighbors. Wafer temperature changes device speed, leakage, analog behavior, and probe geometry. Tests observe faults only when stimulus activates them and responses propagate to measured pins or scan structures. Variation has systematic and random components. Systematic signatures can follow reticle field, wafer radius, scan direction, chamber position, design pattern, power domain, package site, tester, probe card, socket, lot, or time. Random defects can still cluster. Tests observe electrical consequences rather than physical causes, and the same failing signature may arise from several mechanisms. Coverage is conditional on the fault model, activation, propagation, masking, test conditions, and observability. Statistical confidence therefore matters as much as a point estimate, especially for rare defects and small qualification samples.

Architecture, implementation, and production control. The cell integrates prober, chuck, wafer handler, vision alignment, probe card, stiffener and space transformer, interface hardware, ATE, utilities, and datalog. Setup verifies card identity, needle or MEMS condition, planarity, cleaning, continuity, leakage, alignment, touchdown, and correlation units. Test flows often begin with contact and power checks, then parametric, structural, memory, functional, performance, repair, and optional stress steps. Retest policies distinguish contact recovery from true marginal product. Maps preserve coordinates, reticle field, notch orientation, touchdown, site, tester, card, program, limits, and bins. A production flow maintains genealogy from design database and mask revision through wafer, lot, equipment, chamber, recipe, material batch, metrology, probe, assembly, test program, limits, bin, rework, and shipment. Control plans define monitors, sample size, cadence, guardbands, reaction limits, containment, disposition, and escalation. Test limits separate product specification from manufacturing screen and measurement capability. Correlation units, golden devices, calibration, gauge studies, handler/prober checks, and software version control prevent the measurement system from masquerading as product variation.

Applications, alternatives, and economic trade-offs. Wafer sort avoids spending package and assembly cost on known-bad die and is critical when advanced packaging combines multiple costly components. It supports redundancy repair, speed/power grading, known-good-die selection, process excursion detection, and wafer-level reliability screens. Final test after packaging catches assembly faults, package interactions, and conditions unavailable at probe. Some RF or high-power parameters are deferred because wafer probing lacks the final thermal or fixture environment. Wafer-level chip-scale products blur the boundary between sort and final test. The optimal strategy depends on die area, defect opportunity, process maturity, redundancy, package cost, mission profile, repairability, volume, and quality target. High-performance compute may justify expensive known-good-die screening before advanced packaging. Commodity products optimize parallelism and seconds per unit. Automotive, aerospace, medical, and infrastructure applications can require extended traceability and stress evidence. Memory products use redundancy and repair differently from logic. Chiplet systems shift yield from one large die toward several smaller dies but add die-to-die, assembly, thermal, and known-good-die interactions.

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Verification, correlation, and CFS connection. Correlation compares wafer sort with final test and system behavior using stable units across testers, probers, sites, temperatures, and load boards. Escape and overkill analyses identify missing coverage and overly aggressive limits. Probe marks, pad damage, contamination, and card wear are inspected. Measurement capability is proven for low-current, high-speed, and mixed-signal parameters. Test-time optimization removes redundant waits or patterns only after defect-level evidence. Spatial yield signatures are fed back to fab and design teams without losing tester and contact confounders. Verification triangulates inline inspection, physical metrology, electrical process-control monitors, wafer maps, scan diagnosis, memory repair data, parametric distributions, final-test bins, reliability stress, and failure analysis. Pareto charts are stratified by meaningful context before action. Spatial statistics, excursion detection, commonality analysis, design-to-silicon pattern matching, and change-point analysis guide hypotheses. Confirmation requires a controlled fix, predicted signature change, sustained result across enough material, and no adverse shift in other metrics. Raw data and exclusions remain auditable. Acceptance criteria distinguish product specification, manufacturing screen, statistical control, qualification, and customer commitment. Changes to design, process, equipment, interface hardware, test software, limits, or suppliers reopen the assumptions they affect. CFS connects this topic to semiconductor architecture, implementation, verification, manufacturing, packaging, test, and deployed AI-system tradeoffs across the platform.