WAT (Wafer Acceptance Test) performs standardized electrical measurements on test structures to verify that the manufacturing process meets specifications before wafers proceed to packaging. Purpose: Final electrical verification of process quality at wafer level. Gate between wafer fab and assembly/test. Test structures: Located in scribe lines between dies. Include transistors (NMOS, PMOS at various sizes), resistors, capacitors, diodes, contact chains, via chains, metal serpentines. Key measurements: Threshold voltage (Vt), drive current (Idsat/Idlin), off-state leakage (Ioff), gate leakage (Ig), sheet resistance, contact/via resistance, breakdown voltage, junction capacitance, metal resistance. Pass/fail: Each parameter has upper and lower specification limits. Wafers failing critical parameters may be scrapped or held for engineering review. Sampling: Measured on every wafer or every lot depending on fab practice and process maturity. Multiple sites per wafer for uniformity assessment. Data flow: Results feed into SPC system for trend monitoring. Historical data used for process improvement and yield analysis. Correlation to sort yield: WAT parameters correlate with final die sort yield. Predictive models use WAT data to estimate yield before sort. Automation: Fully automated probe systems. Wafer loaded, contacted, measured, and unloaded without operator. Reporting: WAT reports summarize parameter distributions, Cpk values, and pass/fail status per lot. Customer requirements: Customers may specify WAT parameters and limits as part of manufacturing agreement.