Well Proximity Effect (WPE) and Layout-Dependent Effects (LDE) are the systematic variations in transistor characteristics caused by the local layout context surrounding each device — including well edge proximity, STI geometry, and neighboring structures — where seemingly identical transistors can exhibit 10-30mV threshold voltage differences based solely on their placement, requiring layout-aware design methodologies and calibrated SPICE models.

Well Proximity Effect (WPE): Transistors located near the edge of a well implant region experience a different doping profile than those in the center. During ion implantation, the photoresist edge scatters ions laterally, and the implanted dopant diffuses during subsequent anneals. Transistors within ~1-2μm of the well edge have modified V_th (typically higher |V_th| due to additional dopant scattered from the adjacent well implant). The effect decays roughly exponentially with distance from the well edge.

WPE Impact:

STI Stress Effect (LOD — Length of Diffusion): The STI oxide exerts mechanical stress on adjacent silicon active areas. This stress depends on the active area dimensions (LOD — length of diffusion, the distance from the transistor to the nearest STI boundary): closer to STI → more compressive stress → V_th and mobility changes. For PMOS (where compressive stress helps), shorter LOD can actually improve performance, while for NMOS, it may degrade it.

Other Layout-Dependent Effects:

Modeling in SPICE: LDE parameters are included in compact SPICE models (BSIM-CMG, PSP) as instance-specific parameters extracted from the layout: SA (distance to STI on source side), SB (distance to STI on drain side), SCA/SCB/SCC (well proximity model parameters). Layout extraction tools (Calibre, StarRC) automatically compute these parameters for every transistor instance and annotate the extracted netlist.

Design Implications: For matching-critical circuits (current mirrors, differential pairs, DACs, SRAMs), layout-dependent effects demand: symmetric device placement (both devices at same distance from well edge and STI), dummy devices at ends of arrays (to equalize the neighbors), common-centroid layout (to average out systematic gradients), and LDE-aware library characterization (standard cell timing models include LDE sensitivity).

Well proximity effect and layout-dependent effects reveal that transistor performance in modern CMOS is not solely a function of device dimensions but of spatial context — fundamentally connecting physical design (layout) to electrical function and requiring that analog precision and digital timing analysis account for the neighborhood of every transistor on the chip.