Wet Etch Selectivity and Critical Dimension Control

Keywords: wet etch selectivity critical dimension control buffered HF

Wet Etch Selectivity and Critical Dimension Control is the precise management of liquid-phase chemical etching to achieve targeted material removal with high selectivity ratios while maintaining nanometer-scale dimensional accuracy on patterned features — wet etching remains indispensable in CMOS fabrication for cleaning, sacrificial layer removal, surface preparation, and selective material stripping, and its isotropic nature demands careful process engineering to prevent CD loss, undercut, and feature distortion.

Selectivity Fundamentals: Wet etch selectivity is the ratio of etch rates between the target material and surrounding materials. For advanced CMOS, selectivities exceeding 100:1 and sometimes 1000:1 are required. Dilute HF (dHF, typically 100:1 to 1000:1 HF:H2O) etches thermal SiO2 at approximately 2-5 angstroms per second while etching silicon nitride at rates 30-100 times slower, providing adequate selectivity for many applications. Buffered oxide etch (BOE, NH4F:HF mixtures) provides more stable, controlled etch rates compared to dHF through pH buffering. Hot phosphoric acid (H3PO4 at 150-165 degrees Celsius) selectively etches silicon nitride over silicon oxide with selectivities of 30:1 to over 100:1 depending on film quality and temperature control.

CD Control Mechanisms: Since wet etching is isotropic, any vertical etching of a film is accompanied by equal lateral etching (undercut) at feature edges. For a 50-angstrom target overetch into a 500-angstrom film, the lateral undercut adds approximately 50 angstroms of CD loss per side (100 angstroms total). At sub-5 nm nodes where CD tolerances are single nanometers, this undercut must be precisely controlled. Strategies include: minimizing overetch time through tight thickness and etch rate control, using films with inherently lower wet etch rates (high-density PEALD versus PECVD), and employing surfactant-enhanced chemistries that improve wetting uniformity and reduce etch rate variation.

Nanosheet-Specific Challenges: In GAA nanosheet transistors, sacrificial SiGe layers between silicon channels must be selectively removed by wet etching (or vapor-phase etching). Hydrochloric acid/hydrogen peroxide mixtures (SC2-like solutions) or peracetic acid chemistries selectively etch SiGe over Si. The selectivity depends strongly on germanium content: higher Ge percentage increases selectivity but also introduces greater lattice mismatch. Etch uniformity within the narrow gaps between nanosheets requires careful control of solution transport, and surface tension effects can impede penetration into sub-10 nm spaces, necessitating the use of surfactants or megasonic agitation.

Temperature and Concentration Control: Wet etch rates are exponentially dependent on temperature (Arrhenius behavior), making temperature control critical. Modern wet etch tools maintain bath temperatures within plus or minus 0.1 degrees Celsius. For hot phosphoric acid, a 1-degree variation can change the SiN etch rate by 3-5%. Similarly, HF concentration in dHF baths depletes over time as oxide is dissolved, requiring makeup dosing or frequent bath replacement. Inline concentration monitoring using conductivity or refractive index sensors enables closed-loop concentration control.

Megasonic and Spray Processing: Single-wafer spin-process tools deliver etchant to a rotating wafer through a scanning nozzle, providing superior uniformity and CD control compared to batch immersion tanks. Megasonic energy (0.7-3 MHz) enhances mass transport in recessed features and improves etch uniformity without the damage risk of lower-frequency ultrasonics. Spray acid tools combine chemical etching with physical spray momentum for effective residue removal. Each approach trades off throughput (batch processing handles 25-50 wafers simultaneously) against process control (single-wafer provides sub-angstrom repeatability).

Wet etch selectivity and CD control remain essential competencies in CMOS fabrication, with process precision requirements tightening as feature dimensions shrink and three-dimensional device architectures demand uniform material removal within increasingly confined geometries.

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