EUV (Extreme Ultraviolet Lithography) is a next-generation semiconductor manufacturing technology that uses extreme ultraviolet light with a wavelength of 13.5 nm to pattern nanoscale features on silicon wafers.
Fundamental Physics
The resolution limit in optical lithography is governed by the Rayleigh criterion:
``
R = k₁ × λ/NA
Where:
- R = minimum resolvable feature size (nm)
- k₁ = process-dependent coefficient (typically 0.25 - 0.5)
- λ = wavelength of light (nm)
- NA = numerical aperture of the optical system
Wavelength Comparison
| Technology | Wavelength | Ratio to EUV |
|------------|------------|--------------|
| DUV (KrF) | 248 nm | 18.4× |
| DUV (ArF) | 193 nm | 14.3× |
| EUV | 13.5 nm | 1× |
EUV Light Source
EUV light is generated through a Laser-Produced Plasma (LPP) process:
`
EUV Light Generation Process:
1. Tin (Sn) droplets → 25 μm diameter
2. Droplet velocity → 70 m/s
3. CO₂ laser power → 20-30 kW
4. Plasma temperature → 500,000°C
5. Repetition rate → 50,000 Hz
The conversion efficiency from laser power to EUV power:
`
CE = (P_EUV / P_laser) × 100%
Typical values:
- Current systems: CE ≈ 5-6%
- Target EUV power at source: P_EUV ≥ 500 W
Optical System
EUV is absorbed by all materials, requiring reflective optics instead of refractive lenses.
Multilayer Mirror Design uses the Bragg reflection condition:
`
mλ = 2d sin θ
Where:
- m = diffraction order (integer)
- λ = 13.5 nm
- d = bilayer period thickness
- θ = angle of incidence
Mirror Stack Composition:
- Material pair: Molybdenum (Mo) / Silicon (Si)
- Number of bilayers: N ≈ 40-50
- Bilayer period: d ≈ 6.9 nm
- Practical single-mirror reflectivity: R ≈ 67-70%
System transmission with n mirrors:
`
T_total = R^n
For a typical 6-mirror system with R = 0.68:
T_total = (0.68)^6 ≈ 10%
EUV Scanner Specifications
| Parameter | Value |
|------------------------|----------------------|
| Wavelength | 13.5 nm |
| Numerical Aperture | 0.33 |
| Resolution | < 13 nm (half-pitch)|
| Throughput | > 160 wafers/hour |
| Overlay | < 1.4 nm |
| Source Power | ≥ 500 W |
| Machine Weight | ~180 tons |
| Power Consumption | ~1 MW |
| Price | $150-200 million |
High-NA EUV (Next Generation)
| Parameter | Standard EUV | High-NA EUV |
|------------|--------------|-------------|
| NA | 0.33 | 0.55 |
| Resolution | ~13 nm | ~8 nm |
| Price | $150-200M | $350M+ |
Process Nodes Enabled
Timeline of EUV Adoption:
`
2019 │ 7nm (N7+) │ TSMC, Samsung │ Single EUV layer
2020 │ 5nm (N5) │ TSMC, Samsung │ ~14 EUV layers
2022 │ 3nm (N3) │ TSMC, Samsung │ ~20+ EUV layers
2024 │ 2nm (N2) │ Intel, TSMC │ High-NA EUV
2025+│ A14/1.4nm │ TSMC │ High-NA EUV
Challenges
Stochastic Effects at EUV wavelengths, photon shot noise becomes significant:
`
SNR = √N
Where N = number of photons per pixel.
Line Edge Roughness (LER):
`
LER ∝ 1/√Dose
Economic Considerations
Cost per wafer layer comparison:
| Technology | Cost per Layer |
|------------------------|----------------|
| 193i (single) | $15-25 |
| 193i (quad-patterning) | $60-100 |
| EUV (single) | $75-100 |
EUV becomes economical when it replaces 3+ patterning steps.
System Components
`
EUV Lithography System Block Diagram:
Tin Droplet → Laser System → Plasma → EUV Light
Generator (CO₂) (500,000K) (13.5nm)
↓
Wafer ← Projection ← Mask ← Collector
Stage Optics (Reticle) Optics
All components operate in HIGH VACUUM (~10⁻² Pa)
``
Critical Specifications Summary:
- Wavelength: λ = 13.5 nm
- Photon energy: E ≈ 92 eV
- Numerical aperture: NA = 0.33 (standard), 0.55 (High-NA)
- Resolution: R_min ≈ 10-13 nm
- Vacuum requirement: P < 10⁻² Pa
Geopolitical Significance
EUV Supply Chain Chokepoints:
- ASML (Netherlands): Sole EUV system integrator
- Zeiss (Germany): EUV optics (mirrors)
- Cymer/ASML (USA): Light source technology
- Hamamatsu (Japan): Sensors and detectors
- Applied Materials (USA): Mask inspection
Future Roadmap
| Year | Technology | Resolution Target |
|-------|---------------|-------------------|
| 2024 | High-NA EUV | ~8 nm |
| 2027 | Hyper-NA EUV | ~5 nm |
| 2030+ | Beyond EUV | < 3 nm |
EUV lithography represents the most advanced semiconductor manufacturing technology, enabling the production of cutting-edge processors, memory chips, and AI accelerators at 7nm, 5nm, 3nm, and future technology nodes.