White light interferometry is an optical surface profiling technique that uses broadband, low-coherence light to measure 3D surface topography, step heights, and areal surface roughness across semiconductor wafers with sub-nanometer vertical resolution, operating without physical mechanical contact. By splitting a broadband white-light source into a reference optical path directed toward an internal reference mirror and a measurement path directed onto the wafer surface, constructive and destructive optical interference occurs only within an extremely narrow focal depth where the two optical path lengths match within the short coherence length of the source ($L_c \approx 1\text{--}3\ \mu\text{m}$). Combining Coherence Scanning Interferometry (CSI) for macroscopic step heights ($> 100\ \mu\text{m}$) and Phase-Shifting Interferometry (PSI) for smooth sub-nanometer roughness, WLI delivers non-destructive, full-field 3D surface topography maps within seconds.

Broadband low-coherence illumination eliminates the classical $2\pi$ phase ambiguity inherent to laser interferometry. In monochromatic laser interferometers, surface height ($h$) is determined from optical phase ($\phi = 4\pi h / \lambda$). When measuring vertical steps greater than one-quarter of the wavelength ($\Delta h > \lambda / 4$), monochromatic systems suffer from fringe-order ambiguity because phase wraps modulo $2\pi$. In white light interferometry, the broad spectral bandwidth ($\Delta\lambda \approx 100\text{--}200\text{ nm}$) creates a highly localized Gaussian coherence visibility envelope:

where $\lambda_0$ is the central source wavelength ($550\text{ nm}$), $\gamma(z - z_0) = \exp(-(z - z_0)^2 / L_c^2)$ is the spatial coherence envelope, and $L_c$ is the coherence length (typically $1.2\text{--}2.5\ \mu\text{m}$). Peak fringe contrast occurs at the unique spatial coordinate where optical path difference ($\text{OPD}$) between reference and sample beams is exactly zero ($\text{OPD} = 0$), enabling unambiguous step-height measurements from sub-nanometer films to millimeter-tall packaging bumps.

Coherence Scanning Interferometry algorithms extract 3D topography by demodulating the spatial fringe envelope. During measurement, a piezoelectric actuator (PZT) moves the interferometric objective or wafer stage vertically through focus in calibrated nanometer increments ($\Delta z \approx 20\text{--}50\text{ nm}$). For every pixel across the high-speed CMOS sensor ($2048 \times 2048$ array), a discrete digital signal processor performs Hilbert transform demodulation or centroid peak detection on the sampled interferogram:

CSI algorithms achieve vertical height precision below $0.1\text{ nm}$ across arbitrary scan depths ($1\ \mu\text{m}\text{ to }> 10\text{ mm}$), delivering million-point 3D surface topography meshes in under 3 seconds.

Phase-Shifting Interferometry mode delivers sub-angstrom vertical sensitivity for ultra-smooth polished wafers. When measuring ultra-smooth surfaces with root-mean-square roughness $S_a < \lambda / 8$—such as polished silicon wafers, ultra-low expansion (ULE) EUV mirror substrates, or dielectric planarization films—WLI switches to Phase-Shifting Interferometry (PSI) mode. By applying discrete $90^\circ$ phase shifts ($\Delta \phi = \pi/2$) using fine PZT stage steps, surface height is extracted directly from sinusoidal phase shifts:

PSI achieves a vertical noise floor below $0.01\text{ nm}$ ($0.1\text{ \AA}$), resolving atomic-step monolayers and sub-angstrom CMP micro-roughness.

Specialized interferometric objective architectures balance lateral numerical aperture with reference optical paths. Standard optical microscope lenses cannot generate interference without an internal beam splitter. In leading-edge systems, Mirau objectives ($10\times\text{ to }50\times$, $\text{NA} \le 0.55$) incorporate a beam splitter plate and miniature reference mirror within the working distance of the lens, making them ideal for high-resolution semiconductor die inspection. For larger fields of view exceeding $5\text{ mm}$, Michelson objectives use an external beam splitter cube, whereas Linnik objectives match two identical high-NA lenses in sample and reference arms to maximize lateral spatial resolution ($d_{\text{Rayleigh}} \approx 0.35\ \mu\text{m}$) on dense micro-bump arrays.

WLI serves as the primary non-destructive inline tool for 3D packaging, TSV depth, and micro-bump coplanarity. In advanced heterogeneous packaging architectures including CoWoS, InFO, and 3D chiplet stacking, millions of copper micro-bumps and through-silicon vias (TSVs) must maintain strict height coplanarity ($< 0.5\ \mu\text{m}$ total variation) to prevent open-circuit solder failures during thermo-compression bonding. Full-field WLI systems measure height, tilt, and volume distributions across thousands of micro-bumps per field in single-pass area scans, delivering $100\%$ automated wafer-level package disposition.

st=>start: Position wafer under Mirau/Linnik interferometric objective
illum=>operation: Illuminate sample with broad-spectrum LED (λ₀=550nm, Δλ=150nm)
piezo=>operation: Initiate vertical PZT stage scan across calibrated Z-depth range
cmos=>operation: Capture sequence of interference fringe images on 2D CMOS sensor array
envelope=>operation: Compute spatial coherence envelope and extract peak OPD=0 position per pixel
phase=>operation: Apply Phase-Shifting (PSI) algorithm for sub-nanometer height refinement
eval=>condition: 3D step height, bump coplanarity, and Sa roughness within ±0.1nm spec?
pass=>end: Certified 3D surface topography map ready for packaging and process disposition
st->illum->piezo->cmos->envelope->phase->eval
eval(yes)->pass
eval(no)->piezo

Achieving true atomic-scale topography verification requires treating white light interferometry as a broad-spectrum-coherence-envelope-and-phase-interference lens. By unifying short-coherence optical path matching, full-field digital phase analysis, and high-speed multi-scale sensor arrays, WLI delivers non-destructive 3D structural verification from sub-angstrom bare silicon wafer finishes to macro-scale 3D chiplet interconnects. Precision interferometric control ensures that advanced semiconductor processes maintain planarity, structural coplanarity, and high assembly yields across modern microelectronics manufacturing.