Embedded Bridge Interconnect Technology

Embedded Bridge Interconnect Technology refers to silicon bridge dies embedded within organic package substrates to provide high-density die-to-die connections without requiring a full silicon interposer — with Intel's Embedded Multi-die Interconnect Bridge (EMIB) being the leading implementation, offering 2.5D-like interconnect density at lower cost and with better scalability than through-silicon-via-based silicon interposers.

The Problem EMIB Solves:

``
Full silicon interposer (CoWoS-style):
+ High-density interconnect (fine-pitch RDL)
+ Proven for HBM ↔ GPU connection
- Expensive (large Si die, limited to wafer size)
- Large interposer limits package size/yield
- Thermal expansion challenges with large Si

EMIB approach:
+ Small Si bridges only where D2D connections needed
+ Organic substrate for everything else (cheaper)
+ No TSVs in bridge (single-layer RDL)
+ Scalable to large package sizes (many bridges)
- More complex substrate manufacturing
`

EMIB Architecture:

`
Die A Die B
┌───────┐ ┌───────┐
│ │ │ │
│ │ microbumps │ │
└───┬───┘ ↓↓↓↓ └───┬───┘
──────────────┴────────────────────────┴──────── Organic substrate
┌─────────┐
│ EMIB │ ← Small Si bridge (embedded)
│ bridge │ ~4×4mm to 8×12mm
│ (55μm │ 4-layer RDL
│ pitch) │ 55μm bump pitch
└─────────┘
───────────────────────────────────────────── Substrate layers
``

Manufacturing Process:

1. Bridge fabrication: Small silicon die with 2-4 RDL metal layers, fabricated at relaxed node (65nm foundry process). Includes μ-bump pads at 55μm pitch on top surface.
2. Cavity formation: Mill or laser-drill a cavity in the organic laminate substrate at the precise location where the bridge will sit.
3. Bridge placement: Pick-and-place the bridge die into the cavity with <5μm accuracy.
4. Lamination: Build up additional organic substrate layers over the embedded bridge, creating connections from bridge pads to surface pads.
5. Die attachment: Flip-chip bond the chiplet dies onto the package surface, with their edge-facing pads landing on the bridge-connected pads.

Intel Products Using EMIB:

| Product | Application | Bridge Usage |
|---------|------------|-------------|
| Stratix 10 GX | FPGA (2018) | First EMIB product — transceiver tiles |
| Sapphire Rapids HBM | Xeon + HBM | EMIB connects CPU tiles to HBM |
| Ponte Vecchio | GPU/HPC | 47 active tiles, multiple EMIBs |
| Meteor Lake | Client CPU | Foveros + EMIB hybrid packaging |
| Clearwater Forest | Server | Multiple EMIB bridges |

Comparison with CoWoS:

| Feature | Silicon Interposer (CoWoS) | EMIB |
|---------|--------------------------|------|
| D2D pitch | 25-36μm (CoWoS-S) | 55μm |
| BW density | Higher | Moderate |
| Routing layers | 4-6 on interposer | 2-4 on bridge |
| Package size limit | ~100×100mm (reticle) | No Si size limit |
| Cost | Higher (full interposer) | Lower (small bridge) |
| HBM integration | Native | Supported |

Other Bridge Technologies:

- TSMC InFO_LSI: Local silicon interconnect embedded in fan-out package
- Samsung I-Cube4: Bridge approach for HBM connection
- ASE FOCoS-Bridge: Embedded bridge in fan-out package

Embedded bridge technology represents an elegant engineering compromise in advanced packaging — providing chiplet-to-chiplet interconnect density approaching silicon interposer performance but with the cost structure and scalability of organic substrates, making it a key enabler of practical heterogeneous integration for products ranging from client processors to HPC accelerators.