Wire Sag is a wire bonding defect where the wire loop droops below its intended trajectory, risking contact with the die surface or other wires.
What Is Wire Sag?
- Cause: Excessive loop height, inadequate wire tension, thermal softening
- Risk: Short circuits if wire touches die surface or adjacent wires
- Detection: Optical inspection, X-ray for encapsulated packages
- Specification: Minimum clearance typically 50-100μm above die
Why Wire Sag Matters
Modern packages stack multiple die layers with minimal vertical clearance. Sagging wires can cause catastrophic shorts or intermittent failures under thermal cycling.
<svg viewBox="0 0 376 226" xmlns="http://www.w3.org/2000/svg" style="max-width:100%;height:auto" role="img"><rect x="0" y="0" width="376" height="226" rx="12" fill="#0d1117"/><g font-family="ui-monospace,SFMono-Regular,Menlo,Consolas,"Liberation Mono",monospace" font-size="14"><text xml:space="preserve" x="20" y="31.7"><tspan fill="#c9d1d9">Correct Wire Profile:</tspan></text><text xml:space="preserve" x="20" y="50.7"><tspan fill="#c9d1d9"> ╭</tspan><tspan fill="#6e7681">───────────────</tspan><tspan fill="#c9d1d9">╮</tspan></text><text xml:space="preserve" x="20" y="69.7"><tspan fill="#c9d1d9"> </tspan><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9"> Loop apex </tspan><tspan fill="#6e7681">│</tspan></text><text xml:space="preserve" x="20" y="88.7"><tspan fill="#c9d1d9">Die ○ ○ Lead frame</tspan></text><text xml:space="preserve" x="20" y="107.7"><tspan fill="#c9d1d9"> </tspan></text><text xml:space="preserve" x="20" y="126.7"><tspan fill="#c9d1d9">Wire Sag Defect:</tspan></text><text xml:space="preserve" x="20" y="145.7"><tspan fill="#c9d1d9"> ╭</tspan><tspan fill="#6e7681">───</tspan><tspan fill="#c9d1d9">╮</tspan></text><text xml:space="preserve" x="20" y="164.7"><tspan fill="#c9d1d9"> </tspan><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9"> ╰</tspan><tspan fill="#6e7681">─────</tspan><tspan fill="#c9d1d9">╮</tspan></text><text xml:space="preserve" x="20" y="183.7"><tspan fill="#c9d1d9">Die ○ </tspan><tspan fill="#6e7681">↓</tspan><tspan fill="#c9d1d9">sag ○ Lead frame</tspan></text><text xml:space="preserve" x="20" y="202.7"><tspan fill="#c9d1d9"> ████████ </tspan><tspan fill="#6e7681">←</tspan><tspan fill="#c9d1d9"> Die surface contact risk</tspan></text></g></svg>
Prevention Methods:
- Optimize loop profile parameters
- Control bonding temperature precisely
- Use appropriate wire diameter for span length
- Verify wire tensioner settings daily
wire sagbonding defectloop height
Explore 500+ Semiconductor & AI Topics
From EUV lithography to CUDA optimization — search the full knowledge base or chat with our AI assistant.