Yield Enhancement / Yield Ramp — the systematic process of increasing the percentage of functional dies per wafer from initial silicon (often <50%) to production targets (>90%), directly impacting profitability.

Yield Definition

Yield Ramp Phases

1. Technology bring-up: First wafers, yield 0–30%. Focus on getting anything to work 2. Defect learning: Yield 30–60%. Identify and fix systematic defect sources 3. Ramp to production: Yield 60–85%. Optimize process windows, reduce random defects 4. Mature production: Yield 85–95%+. Continuous improvement, excursion monitoring

Yield Loss Categories

• Systematic (design-related): Layout patterns that are hard to manufacture. Fixed by DFM rules
• Random (particle defects): Particles from equipment, chemicals, air. Reduced by cleanroom discipline
• Parametric: Devices work but don't meet specs (speed, power). Caused by process variation

Yield Enhancement Techniques

• Defect inspection + root cause analysis (find the source of particles)
• Process window centering (SPC — Statistical Process Control)
• Equipment maintenance and qualification
• DFM (Design for Manufacturability) rule improvements
• Test coverage improvement (catch more defective dies)

A 1% yield improvement on a high-volume product can mean $10–100M in additional annual revenue — yield engineering is one of the highest-ROI activities in semiconductor manufacturing.