1nm node pathfinding
The 1 nm technology node does not yet have a fixed definition the way earlier nodes did — it is being pathfound, not specified, because the transistor itself must change architecture again before a 1 nm generation can exist at all. Where the 2 nm node substituted gate-all-around nanosheets for finFETs while keeping one planar device per footprint, the 1 nm node is expected to fold two devices into a single vertical column through complementary FET (CFET) integration, push lithography past 0.55 NA into hyper-NA territory, replace copper at the tightest interconnect levels with molybdenum or ruthenium, and move essentially all power delivery to the wafer backside. Each of these is a research-stage capability rather than a qualified production step, which is why 1nm work today is described as pathfinding: multiple candidate architectures are carried forward in parallel, cross-evaluated against manufacturability, and only the surviving combination becomes the qualified node.
**CFET integration is the leading transistor candidate for the 1nm generation, stacking an nMOS device directly above a pMOS device inside a single vertical column.** Rather than placing the two complementary devices side by side as every prior node has done, CFET grows or bonds them on top of one another, sharing a footprint that would otherwise hold only one device. The vertical pitch separating the two tiers runs 30 to 40 nm, and the shared gate region must simultaneously satisfy the work-function and threshold requirements of both an n-type and a p-type channel. This single change is why 1nm is treated as an architecture inflection rather than a dimensional shrink of the 2nm nanosheet.
**Monolithic CFET grows both device tiers from one continuous epitaxial stack, while sequential CFET bonds two separately processed wafers face to face.** The monolithic route keeps the entire stack under a single thermal budget, with peak process temperatures held near 500 °C to avoid degrading the bottom tier while the top tier is formed. The sequential route avoids that thermal conflict by processing each tier independently before wafer bonding, but it introduces a bonding overlay budget below 1.5 nm and a wafer-to-wafer alignment step that has no precedent in front-end logic manufacturing. Neither path is yet qualified, and pathfinding programs at imec and the major foundries are running both in parallel.
**Vertical device stacking compresses standard-cell height by roughly 30 percent but multiplies the electrical coupling between the nMOS and pMOS halves of the cell.** Removing the lateral separation between complementary devices reclaims area directly, but it also means that thermal, mechanical, and electrostatic disturbances in one tier propagate into the other far more readily than in a side-by-side layout. Parasitic capacitance between the tiers, gate-stack sharing, and local heating all become coupled design variables that must be solved together rather than independently.
**Nanosheet thickness inside a 1nm-class CFET column tightens to 4 to 6 nm, and stack uniformity must hold within roughly 0.5 nm across every sheet.** Because both device tiers share the same vertical build, a thickness deviation in one sheet no longer affects a single device — it propagates through the shared gate stack and can shift the threshold voltage of the tier above or below it. Sheet width narrows to 12 to 18 nm, and the epitaxial recipe that forms the alternating channel and sacrificial layers must hold this tolerance across the full stack in one continuous growth run.
**Effective gate length falls to 8 to 10 nm at the 1nm node, a regime where nearly every source of process variation converts directly into threshold-voltage spread.** Subthreshold swing must stay below 66 mV/decade and drain-induced barrier lowering below 22 mV/V, both tighter than the 2nm targets, because the shorter channel gives leakage paths less electrostatic resistance to overcome. Achieving this with two stacked devices sharing thermal and mechanical boundary conditions is substantially harder than achieving it with a single planar nanosheet.
**High-NA EUV at 0.55 NA, only recently qualified for 2nm-class layers, is already approaching its own resolution ceiling for the tightest 1nm critical layers.** The minimum resolvable half-pitch at 0.55 NA sits near 12 nm, which is not fine enough for several of the most demanding 1nm contact and via layers. This has pushed lithography suppliers toward hyper-NA designs above 0.75 NA, with ASML leading the optical and mechanical engineering required to build a lens system at that numerical aperture without an unmanageable increase in tool size or cost.
**Hyper-NA optics shrink the usable exposure field by roughly half relative to 0.55 NA tools, forcing stitching or field-splitting strategies that did not exist at earlier nodes.** A smaller field means a single die may no longer fit within one exposure, so patterns must be split across fields and stitched with sub-nanometer precision, or dies must shrink to fit the smaller field outright. Either path adds design or process complexity that earlier EUV generations never required, and it directly affects wafer throughput and cost per exposed layer.
**Stochastic printing failures, not classical diffraction-limited resolution, are now the dominant lithography risk at 1nm dimensions.** As feature sizes approach the scale of individual EUV photons and resist molecules, random variation in photon absorption and resist blur causes line breaks, bridges, and missing contacts that no amount of optical correction can fully suppress. Research at imec and MIT into resist chemistry and stochastic defect modeling is aimed directly at this problem, targeting a line-edge-roughness figure below 9 Angstrom on the tightest layers.
**Overlay budget compresses below 1.5 nm 3-sigma across the full CFET stack, coupling lithography performance to wafer-level stress control in a way earlier nodes did not require.** Every process step that warps the wafer — deposition stress, anneal, bonding in the sequential CFET path — becomes an overlay error source that must be modeled and corrected. Because the CFET column depends on precise alignment between its two tiers, an overlay excursion no longer degrades one device; it can misalign the shared gate relative to both.
| 1nm pathfinding candidate | Target specification | Primary risk | Leading approach |
|---|---|---|---|
| Transistor architecture | CFET, Lg 8-10 nm | tier-to-tier coupling, thermal budget | monolithic or sequential CFET |
| Lithography | hyper-NA EUV, 0.75+ | smaller field, stochastic defects | ASML hyper-NA optics |
| Overlay | below 1.5 nm 3-sigma | wafer stress, bonding alignment | in-situ correction + metrology |
| Contact metal | Mo / Ru hybrid | rising resistivity at small width | novel low-resistivity metals |
| Power delivery | full backside PDN | wafer thinning, mechanical yield | buried rail plus backside routing |
| Line-edge roughness | below 9 Angstrom | stochastic resist failure | atomic-layer etch, resist chemistry |
| Density gain | 15-20 percent over 2nm | CFET tier coupling | vertical stacking + DTCO |
**Contact resistivity is projected to become the single largest barrier to switching speed at the 1nm node, ahead of gate capacitance itself.** As contact width narrows to 8 to 10 nm, the contact area shrinks faster than the current it must carry, so series resistance climbs even as the transistor's intrinsic switching speed improves. Contact resistance already accounted for roughly a third of on-resistance at 2nm; at 1nm dimensions that share is projected to exceed 45 percent unless the contact metal itself changes.
**Molybdenum and ruthenium are displacing tungsten and even copper at the lowest interconnect levels because their resistivity does not rise as sharply as line width falls.** Copper's resistivity climbs steeply once line width approaches the electron mean free path, and at 1nm dimensions the lowest metal levels sit well inside that regime. Equipment suppliers including Applied Materials, Lam Research, Tokyo Electron, and ASM have introduced deposition and etch processes tuned to these novel metals, targeting void-free fill in contact and via openings with aspect ratios above 4 to 1.
**Backside power delivery, optional at 2nm, becomes structurally necessary at 1nm because front-side routing resources cannot otherwise fit both signal and power wiring.** With the transistor footprint already compressed by CFET stacking, there is no longer room on the front side for a full power grid alongside the signal routing the design needs. Moving the entire power distribution network to the wafer backside, accessed through backside vias roughly 8 nm in diameter, reduces IR drop below 15 mV and frees the front side for signal routing exclusively.
**DTCO at the 1nm node must simultaneously solve the CFET cell architecture, the backside power grid, and the multi-threshold-voltage scheme as one coupled problem rather than three sequential ones.** The cell height achievable depends on the CFET vertical pitch, which depends on the thermal budget of the chosen fabrication route, which in turn constrains how aggressively backside vias can be placed. No single team can optimize any one of these variables without immediately affecting the other two, which is why 1nm pathfinding programs are organized around integrated process-design co-optimization teams rather than separate device and interconnect groups.
**Threshold-voltage engineering multiplies in complexity when the nMOS and pMOS devices share a vertical column and a common gate-stack region.** A modern SoC still needs high, standard, and low threshold-voltage flavors, but at 1nm each flavor must now be realized within a shared gate stack that also has to satisfy the opposite-polarity device in the same column. Work-function metal selection, channel doping, and gate-stack thickness all become joint variables between the two tiers, narrowing the achievable threshold-voltage window even as the number of required flavors stays the same.
```flowchart
1nm node pathfinding flow ──▶ candidate evaluation loop
CFET epitaxy or wafer bonding (monolithic vs sequential)
│
├─▶ channel release + shared gate stack formation
│ Lg 8–10 nm · SS < 66 mV/dec · DIBL < 22 mV/V
│
├─▶ hyper-NA EUV patterning + field-splitting
│ NA > 0.75 · half-pitch < 12 nm · overlay < 1.5 nm
│
├─▶ Mo/Ru contact + interconnect fill
│ void-free 4:1+ aspect ratio · LER < 9 Å
│
├─▶ wafer thinning + backside via + full PDN
│ via ⌀ ~8 nm · IR drop < 15 mV
│
└─▶ DTCO closure + manufacturability scoring
surviving candidate becomes the qualified node
```
**Extreme line-edge roughness control is now a first-order yield lever because a single rough edge can short adjacent nanosheets inside a CFET stack.** Atomic-layer etch processes, which remove material in single-atomic-layer increments rather than continuous plasma exposure, are being evaluated specifically to hold roughness below 9 Angstrom on the tightest 1nm layers. Where earlier nodes could tolerate a few nanometers of edge roughness without functional impact, the shared-column geometry of CFET means the same roughness can now bridge two electrically distinct devices rather than two points on a single device.
**In-line metrology must resolve sub-nanometer features across a full 300 mm wafer without slowing the fab's throughput.** Critical-dimension SEM, scatterometry, and optical overlay metrology all have to operate at a precision that was previously reserved for research-lab characterization tools, and they must do so on every wafer, in line, rather than as a periodic sample. Because the CFET stack hides its lower tier beneath the upper one, several critical dimensions can no longer be measured optically at all, forcing development of new indirect or destructive-sample metrology techniques.
**Mask complexity for 1nm designs is expected to exceed 100 total layers, with a large fraction requiring EUV exposure and several requiring hyper-NA tools specifically.** Every added layer increases both cost and the number of overlay relationships that must be held simultaneously, and the CFET stack's shared gate and backside power layers introduce dependencies between layers that earlier single-tier nodes never had. This raises the bar for up-front design correctness even further than at 2nm, since a single respin now risks disturbing alignment across more interdependent layers.
**Yield learning for 1nm pathfinding programs is measured against research vehicles, not production wafers, because the process itself is still being defined.** Rather than tracking defect density on a fixed process toward a production target, pathfinding teams run controlled experiments that isolate one variable — a metal choice, a thermal budget, an etch chemistry — at a time, comparing candidate combinations against manufacturability scores before any single flow is locked in. This is a fundamentally different kind of yield work than the multi-year ramp campaigns that follow node qualification.
**Channel material exploration beyond strained silicon is one of several parallel tracks carried through 1nm pathfinding, though silicon-based CFET remains the leading near-term candidate.** Germanium channels for the pMOS tier offer higher hole mobility and are being evaluated as a drop-in improvement within an otherwise silicon CFET stack, while two-dimensional channel materials such as transition-metal dichalcogenides are studied at imec, MIT, and Stanford as a longer-horizon path for devices thin enough to avoid the short-channel effects that silicon reaches its limits against. None of these alternate channels is close to displacing silicon at 1nm, but the research keeps a fallback path open if silicon-based scaling stalls.
**Power and leakage trade-offs sharpen further at 1nm, with leakage projected to approach half of total chip power absent aggressive multi-threshold and power-gating strategies.** Short channels leak more by nature, and the tier-to-tier thermal coupling inside a CFET column raises local operating temperature, which further increases subthreshold leakage in a positive-feedback loop that earlier planar and even nanosheet nodes did not experience to the same degree. Holding leakage near 48 percent of total power, rather than letting it exceed half, requires threshold-voltage flavors, power gating, and thermal-aware placement to be co-designed rather than applied as an afterthought.
**The ecosystem coordination required to deliver a 1nm node spans equipment, materials, and design-tool suppliers simultaneously, more so than at any prior node.** ASML carries the hyper-NA lithography risk, Applied Materials, Lam Research, Tokyo Electron, and ASM carry the deposition and etch risk for CFET and the novel contact metals, and imec coordinates much of the pre-competitive research that feeds all of them. Intel, TSMC, Samsung, and IBM each run their own internal pathfinding programs on top of this shared ecosystem, integrating the surviving building blocks into proprietary process flows tuned to their own economics and product mix.
**Reliability characterization for CFET and backside-power structures must be built essentially from scratch because neither structure has volume-manufacturing history.** Electromigration behavior in backside vias, gate-stack reliability under shared-tier thermal and electrical stress, and bonding-interface reliability in the sequential CFET path are all new failure domains. Building the defect and reliability library for these structures — determining what a benign process variation looks like versus what predicts a field failure — is itself a multi-year research program running in parallel with the device work.
**The economics of 1nm pathfinding favor a small number of very large research consortia because no single company can carry every parallel candidate track alone.** The combined cost of hyper-NA tool development, CFET process research, novel-metal qualification, and backside-power integration exceeds what any individual foundry or IDM can justify funding in isolation before a qualified node even exists. This is why pre-competitive research consortia such as imec, working alongside equipment suppliers and the leading foundries, carry a disproportionate share of the earliest 1nm pathfinding work.
**Every 1nm candidate architecture is still being weighed against a common set of manufacturability criteria before any single combination is locked in as the qualified node.** Yield potential, cost per wafer, reliability risk, and design-tool readiness are scored against each other for every candidate — monolithic versus sequential CFET, 0.55 NA versus hyper-NA lithography, molybdenum versus ruthenium contacts — and the surviving combination is not necessarily the one with the best individual performance but the one that clears every gate simultaneously. This is the essence of pathfinding: elimination through coupled constraints rather than optimization of any single metric.
Read the 1nm node through a coupled-systems lens: CFET architecture, hyper-NA lithography, contact and interconnect metallurgy, and backside power delivery cannot be pathfound independently, because a change in any one reshapes the manufacturability and electrical budget of all the others, and the 1nm node becomes real only once metrology, yield learning, and DTCO converge on one mutually consistent combination.
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## Appendix: Pathfinding Reference and Candidate Comparison
**Dimensional scaling at the 1nm node pushes gate length, nanosheet thickness, and overlay budget to roughly 0.7 times their 2nm values simultaneously.** This uniform scaling factor is deceptively simple to state but requires coordinated advances in lithography, deposition, and etch, because no single tool or material change delivers 0.7 times scaling on its own across every dimension at once.
**The CFET route chosen — monolithic or sequential — determines much of the rest of the 1nm process flow, from thermal budget to bonding metrology to contact strategy.** Because this single architectural decision cascades into nearly every other process module, it is treated as the highest-priority open question in current 1nm pathfinding programs at Intel, TSMC, Samsung, and IBM alike.
**Backside power delivery and novel contact metals are development programs that reduce risk for each other, since a lower-resistance contact reduces the current a backside via must carry, and a lower-resistance backside grid reduces the voltage margin needed at the contact.** Coordinating these two programs, rather than qualifying them independently, is expected to shorten the overall path to a manufacturable 1nm node.