process node

**Process Node (Technology Node)** — a naming convention indicating the generation of semiconductor manufacturing technology, historically tied to minimum feature size but now largely a marketing designation. **Historical Meaning** - Originally referred to the physical gate length of transistors - 180nm node had ~180nm gate length. Direct correspondence - Correlation broke down below 28nm — "7nm" gates aren't 7nm **Modern Reality** - Node names are marketing terms indicating relative density improvement - TSMC "5nm" (N5): ~173M transistors/mm$^2$ - TSMC "3nm" (N3): ~292M transistors/mm$^2$ - Intel renamed: Intel 7 ≈ TSMC 7nm density, Intel 4 ≈ TSMC 5nm **What Actually Scales** - Transistor density (primary metric) - Metal pitch (affects routing density) - Contacted poly pitch (CPP) - Minimum metal pitch (MMP) **Node Roadmap (2024-2028)** - 3nm: TSMC N3, Samsung 3GAE (current production) - 2nm: TSMC N2, Intel 20A, Samsung 2GAP (2025-2026) — GAA transistors - 1.4nm (A14): Intel 14A (2027+) — backside power delivery **Process nodes** drive the industry forward, but comparing across foundries requires looking at actual density metrics, not node names.