semiconductor process node naming

**Semiconductor Process Node Naming Conventions — From Physical Dimensions to Marketing Designations** Semiconductor process node names have evolved from direct physical measurements to increasingly abstract marketing designations that no longer correspond to any single transistor feature size. Understanding the history and current state of node naming — and the metrics that actually matter — is essential for accurately comparing technologies across foundries and generations. **Historical Node Naming** — When names matched physical dimensions: - **Early planar CMOS nodes** (1 μm through 130 nm) named their process generations after the minimum metal half-pitch or physical gate length, providing a direct correlation between the node name and measurable transistor features - **Gate length scaling** drove performance improvements as shorter channels increased transistor switching speed and reduced capacitance, making gate length the natural metric for technology comparison - **Dennard scaling** predicted that as transistors shrank, voltage and current would scale proportionally, maintaining constant power density — a relationship that held through approximately the 90 nm generation - **Contact pitch and metal pitch** also scaled in rough proportion to the node name, maintaining consistency between the marketing designation and actual physical dimensions **The Naming Divergence** — When node names became decoupled from reality: - **Below 90 nm** foundries began using names that no longer matched any single physical dimension - **FinFET introduction at 22/14 nm** made gate length less meaningful since the channel is defined by fin width and height - **Competitive marketing pressure** incentivized aggressive node names, with TSMC and Samsung "7 nm" representing different physical dimensions - **Intel's naming reset** renamed its 10 nm Enhanced SuperFin to "Intel 7" to better align with competitor conventions **Meaningful Comparison Metrics** — What actually defines technology capability: - **Transistor density** measured in millions of transistors per square millimeter (MTr/mm²) provides the most direct comparison of packing efficiency across foundries and nodes - **Logic cell density** using standard cell libraries (e.g., high-density SRAM or logic gate arrays) accounts for both transistor size and interconnect routing overhead - **Contacted poly pitch (CPP)** measures the repeating distance between adjacent transistor gates, directly impacting logic density and scaling trajectory - **Minimum metal pitch (MMP)** defines the tightest interconnect routing capability, often the limiting factor for area scaling at advanced nodes - **Gate-all-around (GAA) nanosheet width** and stack count become relevant metrics at 3 nm and below, where channel dimensions determine drive current and performance **Current Node Landscape and Future Trajectory** — Modern naming in context: - **TSMC N3/N3E** and Samsung 3GAE represent the current leading edge with transistor densities approaching 300 MTr/mm² - **Angstrom-era naming** (Intel 20A, TSMC A16) signals the transition to sub-2 nm equivalent nodes using gate-all-around nanosheet transistors - **IRDS** attempts to standardize technology benchmarking through defined metrics rather than node names - **Application-specific relevance** means the "best" node depends on the product — leading-edge density matters for mobile processors while analog performance may peak at larger nodes **Semiconductor node naming conventions serve primarily as marketing shorthand, making it essential to evaluate actual transistor density, pitch dimensions, and performance metrics when comparing technologies across the foundry landscape.**