semiconductor process node naming

Semiconductor process node names are marketing labels that only loosely describe transistor size. **A node name is not a ruler.** TSMC N3, Samsung 3 nm, Intel 18A, and older 14 nm or 7 nm labels cannot be compared by the number alone. Real comparisons require density, performance, power, SRAM behavior, interconnect stack, design rules, yield, voltage range, libraries, and packaging ecosystem. | Comparison metric | What it reveals | Why node name alone misses it | |---|---|---| | Logic density | How many standard cells fit in an area | Libraries and design rules change the result | | SRAM density | Memory bitcell scaling | SRAM often scales differently from logic | | Performance and power | Speed at a given voltage or power | Depends on devices, wires, and libraries | | Yield and maturity | How many good die emerge | A dense node can still be commercially weak | | Ecosystem readiness | IP, tools, packaging, and sign-off support | Product teams need more than transistors | **Foundry process comparison is therefore contextual.** The best node for a chip is the one that meets product goals with acceptable cost, schedule, yield, IP availability, and supply confidence.