FinFET transistor technology

**FinFET (Fin Field-Effect Transistor) Technology** is the **3D transistor architecture that replaced planar MOSFETs at the 22/16/14 nm nodes — wrapping the gate around a thin vertical silicon fin on three sides (tri-gate) to provide superior electrostatic control over the channel, dramatically reducing short-channel effects and leakage current that made planar transistor scaling below 28 nm economically impractical**. **Why FinFET** As planar transistors scaled below 28 nm, the gate's control over the channel weakened: the drain electric field penetrated through the thin channel (drain-induced barrier lowering — DIBL), causing excessive leakage current and threshold voltage roll-off. The gate controlled only the top surface of a wide, shallow channel. FinFET's solution: make the channel a tall, thin fin — the gate wraps around three sides, providing 2-3× more gate-to-channel coupling per unit footprint. **FinFET Structure** ``` Gate Metal | | | | _____|__|__|__|_____ | | Fin | | |Gate | (Si) |Gate | | |_______| | |_____|_______|_____| | BOX / STI oxide ``` - **Fin Width**: 5-7 nm at leading nodes (determines electrostatic integrity). Narrower = better control but higher resistance. - **Fin Height**: 40-55 nm. Taller fins provide more drive current per footprint (more gate-channel contact area). - **Fin Pitch**: 25-30 nm at 5 nm node. Determines device density. - **Effective Width**: W_eff = 2 × fin_height + fin_width (tri-gate contribution). A single fin provides ~90-120 nm of effective channel width. - **Multi-Fin Devices**: Standard cells use 1-4 fins per transistor. More fins = higher drive current = faster switching but larger area. **FinFET Process Challenges** - **Fin Patterning**: Fins at <30 nm pitch require multi-patterning (SADP/SAQP with DUV or single-pass EUV). Fin width uniformity <1 nm variation is critical — a 1 nm fin width change shifts V_TH by ~30 mV. - **Fin Reveal/Recess**: After fin patterning, STI oxide fills the space between fins, then is recessed to expose the upper portion of the fin (the channel region). Recess depth uniformity directly controls device characteristics. - **Replacement Metal Gate (RMG)**: A dummy polysilicon gate is formed first, then removed after S/D epitaxy and ILD deposition, and replaced with high-k dielectric + work function metals. The gate-last process avoids damaging the high-k dielectric during high-temperature S/D processing. - **S/D Epitaxy**: Epitaxial SiGe (PMOS) or Si:P (NMOS) grows from the fin surface to form source/drain regions. The epitaxial shape and volume control both contact resistance and channel strain. **FinFET Scaling Limits** At ~3 nm node, FinFET encounters fundamental limits: - Fin width below 5 nm causes quantum confinement and excessive resistance. - Single-fin drive current is insufficient for high-performance logic. - GAA (Gate-All-Around) nanosheets succeed FinFET, providing 4-side gate control and adjustable channel width through stacked sheet geometry. FinFET Technology is **the 3D transistor innovation that extended Moore's Law for a decade** — the architectural leap from planar to vertical channel geometry that enabled five generations of scaling (22 nm to 3 nm) and billions of devices in production, before passing the baton to its successor, the Gate-All-Around nanosheet transistor.