fin patterning finfet

**Fin Patterning for FinFET Fabrication** is the **critical lithography and etch sequence that defines the ultra-narrow, tall silicon fins (width 5-7 nm, height 40-55 nm at sub-7nm nodes) from the bulk silicon substrate — where sub-nanometer control of fin width uniformity across the entire wafer directly determines transistor drive current, threshold voltage, and leakage uniformity**. **Why Fin Patterning Is the Hardest Step** The fin is the transistor channel. Its width determines the volume of silicon available for current flow, and because the gate wraps around all three sides, even 0.5 nm of fin width variation causes measurable Vth shift. At 5nm-class technology, the fin pitch (distance between adjacent fins) is 25-30 nm — far below the resolution limit of single-exposure 193nm immersion lithography. **Patterning Approaches** - **Self-Aligned Double Patterning (SADP)**: A mandrel is patterned at 2x the final fin pitch. Conformal spacers are deposited on the mandrel sidewalls. The mandrel is selectively removed, leaving the spacers as the etch mask at half the original pitch. SADP is the standard for fin patterning at 14nm through 5nm nodes. - **Self-Aligned Quadruple Patterning (SAQP)**: SADP is performed twice in sequence — spacers from the first SADP serve as mandrels for a second spacer deposition and mandrel pull. This achieves quarter-pitch resolution, enabling the sub-30nm fin pitches required at 3nm and below. - **EUV Direct Print**: At 3nm and below, some foundries print fins directly with single-exposure EUV lithography (13.5 nm wavelength), eliminating the multi-step SADP/SAQP flow. The tradeoff: EUV stochastic defects (line-edge roughness, missing/bridging features) at tight pitches remain a yield challenge. **Etch Challenges** - **Fin Height Uniformity**: The silicon etch that transfers the pattern into the substrate must maintain etch depth uniformity within ±1 nm across the wafer. Loading effects (etch rate variation with local pattern density) require gas-flow and plasma-power tuning. - **Fin Profile Control**: Perfectly vertical sidewalls are essential. A tapered fin (wider at base, narrower at top) means the gate wraps differently at different heights, degrading electrostatic control. Chlorine/HBr-based plasma chemistries with precise passivation control maintain >89° sidewall angles. - **Fin Reveal (Recess Etch)**: After STI oxide deposition and CMP, the oxide between fins is recessed to expose the fin height that becomes the active channel. The recess depth directly sets the effective fin height — and hence the drive current per fin. Fin Patterning is **the defining process challenge of the FinFET era** — transforming flat silicon into a forest of perfectly uniform, nanometer-scale vertical blades that serve as the channels for every transistor on the chip.