FinFET transistor technology
**FinFET Transistor Technology** is **the 3D transistor architecture where the channel is formed on a thin vertical silicon fin wrapped by the gate on three sides — providing superior electrostatic control over the channel compared to planar MOSFETs, enabling continued voltage and dimension scaling from the 22nm through 5nm technology nodes with dramatically reduced leakage current and improved performance**.
**FinFET Structure:**
- **Silicon Fin**: thin vertical fin of silicon (width 5-10 nm, height 30-50 nm) standing on the substrate — fin width determines the effective channel width; multiple fins connected in parallel for higher drive current
- **Tri-Gate Configuration**: gate wraps around three sides (top and both sidewalls) of the fin — three-sided gate control provides 2-3× better electrostatic integrity compared to single-gate planar transistor; subthreshold swing approaches ideal 60 mV/decade
- **Fin Pitch**: spacing between adjacent fins — 20-30 nm at 7nm node; determines the transistor density; fin depopulation (removing fins from standard cell) controls drive strength granularity
- **Quantized Width**: channel width = N_fins × (2×H_fin + W_fin) — only integer number of fins possible, creating discrete rather than continuous width choices; design must accommodate quantized drive strength
**Process Flow Differences:**
- **Fin Patterning**: self-aligned double or quadruple patterning (SADP/SAQP) creates sub-litho fin pitch — mandrel-spacer approach achieves pitches below resolution limit of single-exposure lithography; fin height and profile uniformity critical for matching
- **STI Recess**: shallow trench isolation oxide etched back to expose fin above isolation — recess depth controls effective fin height and thus channel width; precise recess control (<1 nm variation) required for performance uniformity
- **Gate Last (Replacement Metal Gate)**: fin formation → dummy poly gate → source/drain epitaxy → ILD deposition → dummy gate removal → high-k/metal gate fill — gate-last process avoids high-k damage during source/drain anneal
- **Source/Drain Epitaxy**: epitaxial SiGe (PMOS) or SiP (NMOS) grown on fin creates raised source/drain — merged epitaxy between adjacent fins increases contact area and reduces resistance; strain engineering enhances carrier mobility
**FinFET Advantages:**
- **Leakage Reduction**: 3D gate control reduces short-channel effects — subthreshold leakage 100-1000× lower than planar at equivalent gate length; enables lower operating voltage (0.7-0.8V vs. 1.0V for planar)
- **Performance**: 15-20% speed improvement at same power, or 50% power reduction at same speed compared to predecessor planar node — improved electrostatics enable more aggressive gate length scaling
- **DIBL (Drain-Induced Barrier Lowering)**: FinFET DIBL typically 20-50 mV/V compared to 100-200 mV/V for planar — superior channel control reduces threshold voltage sensitivity to drain voltage
- **Variability**: thin-body channel (fully depleted) eliminates random dopant fluctuation — major source of variability in planar MOSFETs; FinFET variability dominated by fin width and LER (line edge roughness)
**FinFET technology has been the workhorse transistor architecture from Intel's 22nm (2012) through TSMC/Samsung 5nm (2020) — enabling over a decade of continued Moore's Law scaling before being succeeded by Gate-All-Around (GAA) nanosheet transistors at 3nm and below, which extend the multi-gate concept to full 360° gate control around horizontal nanosheets.**