20nm-Process
A 20 nm process is a logic-manufacturing generation whose implementation must be identified by supplier. In TSMC’s historical sequence, 20SoC is associated with planar logic before its 16 nm FinFET platforms. The distinction shows that a smaller node label and a new transistor architecture are different development decisions. Device structure should be named explicitly.
TSMC’s period reports distinguish 20SoC production from the later FinFET ramp. Its 2015 business review describes 20SoC volume production and dates 16FF+ volume production to mid-2015. These records establish a sequence of named platforms rather than a universal industry calendar. A roadmap target and achieved manufacturing status remain different kinds of evidence.
Dense planar logic placed substantial demands on patterning and leakage control. Short channels require careful electrostatics, while closely spaced patterns restrict the optical process window. Multiple patterning can divide a dense layout into manufacturable steps at the cost of additional masks, alignment, and integration work. The exact layer strategy belongs to the specific process flow.
Wiring does not scale in the same way as every transistor parameter. Line resistance, coupling capacitance, vias, and routing restrictions influence cell and chip performance. A reduced nominal generation can therefore deliver different benefits for logic, SRAM, analog, and I/O. Physical implementation is needed to connect process capability to usable product density.
The historical role of 20 nm is clearer when separated from FinFET naming. A manufacturer can introduce a fin-based front end while retaining or adapting parts of an earlier wiring platform. Product migration then requires new device models and libraries as well as compatible interconnect rules. The node is best understood as an integrated platform in that broader transition.
Sources and further reading. [TSMC 2015 technology and business review](https://investor.tsmc.com/static/annualReports/2015/english/e_2_2.html); [TSMC 2014 technology review](https://investor.tsmc.com/static/annualReports/2014/english/e_5_2.html).
Read 20 nm process as a planar-logic generation whose patterning and wiring demands helped frame the subsequent foundry FinFET transition.