3D NAND Staircase Etch

3D NAND staircase etch spends more process time than almost any other single etch module in the flow, because every one of the 200 to 300-plus word lines buried in the ONON film stack needs its own electrical contact landing at its own depth, and a flat etch step cannot produce 200 to 300-plus different depths at once.

Stack ready
ONON film stack + hard mask
Staircase mask set
zone plan: single or chopped
Trim-etch looprepeated dozens of cycles
Resist trim
mask narrows one increment
ON-pair etch
one or more layers removed
Depth check
metrology confirms step depth
↻ next step
Step etch
exposes SiN landing pad
Oxide fill, CMP, recess
staircase-oxide recess
Word-line contact etch next
lands on each exposed step

The trick that makes this affordable is trimming the mask, not re-masking the wafer, for every one of those depths.

3D NAND Staircase Etch — One Landing Per Word Line a trim-etch loop carved into the same ONON stack the film-stack step deposited Word Line Contacts (WLC) land here — a different depth on every step photoresist mask — trimmed narrower before each etch cycle Trim-etch loop 1. Trim resist narrower 2. Etch one ON pair 3. Repeat, dozens of times chop/split-zone etch: multiple depths per cycle, fewer total cycles needed step etch exposes the SiN landing on each stair 200-300+ layers Why the staircase outlasts every other etch module in cycle time a flat chip needs one contact etch; this stack needs 200 to 300+ of them, each landing on a different step with a different exposed SiN thickness — one trim-etch cycle per step, or several steps per cycle if zones are chopped, but never fewer cycles than the layer count divided by the zone count. after etch: thick oxide gap-fill, CMP, then a staircase-oxide recess exposes each landing pad for the word-line contact etch

The core cycle is a photoresist trim-etch loop, also just called "stair etch." Each pass trims the resist mask narrower by one increment, then etches through one ON pair (or more) of the stack underneath, so the exposed area shrinks by one step every cycle — repeated dozens of times to carve dozens to hundreds of landings into a single stack, without ever stripping and remasking between cycles.

Multi-zone, or chopped, staircase etch cuts the cycle count down by splitting the staircase into several zones and etching more than one depth per cycle (chop etch, split-zone staircase) — the practical response to layer counts climbing from 128 to 200 to 300-plus across Samsung's V-NAND, SK hynix's 4D NAND, Kioxia/WD's BiCS, Micron's replacement-gate generations, and YMTC's Xtacking, where a strict one-cycle-per-layer loop would simply take too long to run in production.

A step etch finishes each landing by exposing the SiN pad the eventual word-line contact etch will stop on, and once the full staircase shape is cut, a thick gap-fill oxide is deposited over the whole structure and planarized by CMP before a staircase-oxide recess re-exposes every landing pad at its correct depth.

Getting this wrong does not show up until the contact etch runs much later in the flow. A staircase step that lands a few nanometers off target becomes a word-line contact with too little or too much overetch margin on that specific layer — which is why staircase depth is tracked with in-line metrology after every trim-etch cycle, not just checked once at the end.

The staircase is the one etch module in 3D NAND whose entire job is converting a vertical layer count into a horizontal landing surface: every number that defines the chip — 128 layers, 176, 236, 300-plus — is also, directly, the number of trim-etch cycles (divided by however many zones are chopped together) that this single module has to run before a word-line contact can reach any of them.

Take 3d nand staircase etch further

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