400-Layer 3D NAND

400-Layer 3D NAND Flash represents the frontier of solid-state storage density, pushing non-volatile memory far beyond the planar scaling limits that halted 2D NAND a decade ago. Leading memory manufacturers — Samsung (V-NAND Gen 10/11), SK hynix (321-layer and 400-layer 4D NAND), Micron, and Kioxia/Western Digital (BiCS9/10) — are transitioning from 200+ layer architectures to vertical stacks exceeding 400 active wordline layers. Reaching 400 layers requires conquering the most brutal physics challenge in semiconductor manufacturing: etching microscopic memory holes through an alternating superlattice of oxide and nitride films with an aspect ratio approaching 100:1, while integrating peripheral CMOS drive circuits directly beneath the memory array using CMOS Under Array (CUA) and multi-tier string stacking.

The physics barrier: High Aspect Ratio (HAR) etching. In 3D NAND, memory cells are formed by depositing hundreds of alternating thin films of silicon dioxide ($SiO_2$) and silicon nitride ($Si_3N_4$) (the ONON stack). Vertical channel holes must then be etched straight down through the entire stack in a single reactive ion etch (RIE) plasma process before the nitride is stripped and replaced with tungsten wordlines. The aspect ratio of the hole follows:

At 400 layers, with each alternating tier measuring roughly 25 to 30 nm, the total vertical stack height $D_{stack}$ exceeds 10 to 12 µm. If the top hole diameter $d_{hole}$ is roughly 100 nm to maintain bit density, the aspect ratio ($AR$) reaches $80:1\text{ to }100:1$. In a conventional room-temperature plasma etch, reactive radicals cannot penetrate 10 microns down a narrow 100 nm shaft without bouncing off sidewalls, causing severe bowing (bulging in the middle), twisting, or incomplete etching at the bottom (tapering).

The breakthrough: cryogenic etching and string stacking. Foundries solve the HAR etching barrier through two complementary innovations:
1. Cryogenic Plasma Etching: By cooling the electrostatic wafer chuck down to $-60\text{ \textdegree C}\text{ to }-100\text{ \textdegree C}$ during plasma etch using fluorocarbon ($C_4F_8, C_4F_6, NF_3$) chemistry, passivating fluorocarbon polymer films instantly freeze onto the sidewalls of the hole. This chemical freeze prevents lateral ion etching, producing perfectly vertical channel holes with zero bowing and allowing etching rates to increase by $3\times$.
2. String Stacking (Multi-Tier Architecture): Instead of attempting to drill 400 layers in a single impossible pass, manufacturers split the array into two or three stacked tiers. In a triple-stack architecture, an initial tier of ~135 layers is deposited and etched; a second tier of ~135 layers is deposited on top and etched to align with the lower holes; followed by a third tier. Achieving this requires atomic overlay alignment (<2 nm) between tiers to prevent electrical disconnection between channel polysilicon plugs.

CMOS Under Array (CUA) and wafer bonding. In early 3D NAND, the peripheral CMOS circuitry (page buffers, row decoders, charge pumps) sat beside the memory array, consuming over 25% of the total chip area. Modern 400-layer architectures utilize CMOS Under Array (CUA) &#8212; also called Cell on Periphery (COP) or Xtacking. The peripheral control transistors are fabricated on the silicon wafer first. The 400-layer memory superlattice is then built directly on top of the CMOS circuitry. In advanced implementations (like YMTC Xtacking and future Kioxia architectures), the CMOS logic wafer and the 3D NAND array wafer are fabricated in separate fabs and bonded face-to-face via bumpless Cu-Cu hybrid bonding, maximizing both logic speed and NAND array thermal budget.