90nm-Process

The 90 nm process generation brought strain engineering into prominent commercial CMOS implementations. A node label still describes a family of coordinated manufacturing capabilities rather than one universal gate length. Different companies could use different substrates, wiring stacks, and device structures within the same nominal generation. Those implementation choices matter when comparing products.

A 2004 Intel-authored paper documents strained silicon in a 90 nm logic technology. Thompson and colleagues describe selective silicon-germanium source/drain regions for p-channel devices and a tensile nitride capping layer for n-channel devices. The techniques alter strain in the silicon channel. They improve carrier transport through materials and mechanical engineering rather than through geometric shrinking alone.

90 nm process Conceptual comparison; not a manufacturing specification or scale drawing Node name 90 nm technology generation Not every feature is 90 nm Published example 45 nm gate length Intel-authored 2004 paper Strain techniques pMOS: embedded SiGe nMOS: tensile nitride cap The 90 nm generation and a 45 nm transistor gate length can describe the same documented process.

The paper’s device dimensions illustrate why node and gate length need separate labels. It describes 45 nm gate-length transistors in the 90 nm technology. The two numbers refer to different aspects of the implementation. Treating 90 nm as the literal length of every transistor would therefore misrepresent even a documented process from that generation.

Leakage and switching power constrained the benefit of additional density. Short channels complicate electrostatic control, while thin gate insulation can permit substantial tunneling. Reducing supply voltage helps switching energy but also affects speed and noise margins. A successful technology balances drive current, leakage, variability, and reliability for its intended product range.

The historical significance is the increasing importance of engineered materials. Strain, low-k wiring insulation, and process integration extended performance beyond what a simple geometric scale factor predicts. Circuit designers still needed qualified models and libraries to realize those benefits. The generation is best understood through named process implementations and measured trade-offs.

Sources and further reading. [Thompson et al., A Logic Nanotechnology Featuring Strained-Silicon, 2004](https://doi.org/10.1109/LED.2004.825195); [Intel 65 nm SRAM demonstration, November 2003](https://www.intel.com/pressroom/archive/releases/2003/20031124tech.htm).

Read 90 nm process as a generation in which process-induced channel strain became an important extension of CMOS scaling.

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