adc design architecture sar

**ADC Design Architectures** are **the circuit topologies that convert continuous analog signals into discrete digital codes, with SAR, pipeline, and sigma-delta representing the three dominant architectures each optimizing different trade-offs between speed, resolution, power, and area**. **SAR ADC Architecture:** - **Binary Search Algorithm**: the SAR ADC successively approximates the input voltage by testing one bit per clock cycle from MSB to LSB using a DAC and comparator — an N-bit conversion requires N comparison cycles plus sampling - **Capacitive DAC**: charge-redistribution DAC using binary-weighted capacitor array eliminates resistor matching requirements — total capacitance scales as 2^N × unit capacitor, limiting practical resolution to 16-18 bits - **Comparator Design**: dynamic comparator (StrongARM latch) dissipates power only during comparison — kickback noise from comparator switching couples into the DAC and must be minimized through careful layout and timing - **Performance Range**: SAR ADCs achieve 8-18 bit resolution at 1-500 MSPS with power consumption from microwatts to tens of milliwatts — dominant architecture for IoT, sensor interfaces, and moderate-speed applications **Pipeline ADC Architecture:** - **Stage-Based Processing**: each pipeline stage resolves 1-3 bits, subtracts the quantized value from the input, and amplifies the residue by 2^k for the next stage — stages operate concurrently on different samples achieving one sample per clock cycle throughput - **Residue Amplifier**: the multiplying DAC (MDAC) combines subtraction and amplification using switched-capacitor circuits — op-amp gain, bandwidth, and settling accuracy directly limit achievable resolution - **Digital Error Correction**: redundant bits (1.5-bit/stage architecture) allow comparator offsets up to ±Vref/4 without causing missing codes — digital backend aligns and corrects stage outputs - **Performance Range**: 8-16 bit resolution at 50 MSPS to 1+ GSPS — used in communications receivers, radar, and high-speed data acquisition **Sigma-Delta ADC Architecture:** - **Oversampling Principle**: samples the input at many times the Nyquist rate (OSR = 32-256×) and uses noise shaping to push quantization noise out of the signal band — achieves very high resolution (20-32 bits) with relaxed component matching - **Modulator Order**: first-order modulators shape noise with a 20 dB/decade slope; higher-order (2nd-5th) modulators achieve steeper noise shaping but require careful stability analysis — CIFB and CIFF topologies common - **Decimation Filter**: digital low-pass filter and downsampler removes out-of-band shaped noise and reduces output data rate — CIC filters followed by FIR compensation are standard implementations - **Performance Range**: 16-32 bit resolution at 1 kHz to 10 MHz bandwidth — dominant for audio, precision measurement, and sensor conditioning **Key Design Metrics:** - **DNL/INL**: differential and integral nonlinearity measure code-to-code and cumulative deviation from ideal transfer function — DNL < ±0.5 LSB guarantees no missing codes - **SFDR/SNDR**: spurious-free dynamic range and signal-to-noise-and-distortion ratio characterize spectral performance — SFDR >80 dB required for communications - **Power Figure of Merit**: Walden FoM (energy per conversion step) = Power/(2^ENOB × fs) — state-of-art SAR ADCs achieve <1 fJ/conversion-step - **Calibration**: foreground (interrupts conversion) and background (transparent) calibration techniques correct capacitor mismatch, gain errors, and timing skew **ADC architecture selection is fundamentally driven by the application's resolution-bandwidth product, with SAR dominating the moderate-speed sweet spot, pipeline excelling at high speed, and sigma-delta achieving unmatched resolution at lower bandwidths.**