analog to digital converter

**An analog-to-digital converter (ADC)** translates a continuous-amplitude analog signal into a sequence of discrete binary codes, placing the analog-digital boundary at every point where a physical measurement or RF signal must enter a digital processing system. Resolution (bits), sample rate (samples per second), power consumption, and linearity define the trade-space that makes ADC design one of the most challenging disciplines in mixed-signal IC design. ```svg Analog-to-Digital Converter (ADC) converts a continuous analog signal into a discrete digital code — resolution, speed, and power define the design trade-space ADC Architecture Families Flash ADC 2^N comparators in parallel; fastest (GS/s); high power + area; 4-8 bit Pipeline ADC cascaded 1.5-bit stages; 10-14 bit, 10-500 MS/s; Wi-Fi, cable, video SAR ADC (successive approximation) DAC + comparator + logic; 8-18 bit, 1-100 MS/s; lowest power; IoT, wearables Sigma-Delta (oversampling) 1-bit quantizer + decimation filter; 16-24 bit; audio, precision sensors Speed vs resolution trade-off (Walden FOM): Flash: GS/s, 4-8 bit Pipeline: 100MS/s, 10-14 bit SAR: 10MS/s, 16 bit SD: kS/s, 20-24 bit ENOB drops ~1 bit per 2x frequency increase (thermal noise) SAR ADC — Binary Search Sample + Hold Comparator SAR Logic Capacitor DAC 4-bit binary search example (Vin = 0.6 Vref): Step 1: DAC=0.5? Vin>DAC → bit3=1, try 0.75 Step 2: DAC=0.75? Vin<DAC → bit2=0, try 0.625 Step 3: DAC=0.625? Vin<DAC → bit1=0, try 0.5625 Step 4: DAC=0.5625? Vin>DAC → bit0=1 → code=1001 N comparisons for N-bit result — power O(N), not O(2^N) Capacitor DAC: binary-weighted C array, no resistors needed Noise: kT/C limits SNR — larger C = lower noise, more area Key Metrics & Sigma-Delta Performance metrics: Metric Definition ENOB Effective number of bits SNDR / SINAD Signal / (noise+distortion) SFDR Spurious-free dynamic range Walden FOM P / (2·ENOB · fs) INL / DNL Integral / diff nonlinearity Sigma-Delta concept: Vin → [+] → integrator → 1-bit Q → bitstream ↑ ↓ 1-bit DAC feedback (noise-shaping loop) Oversampling (256x) + decimation filter → 24-bit output ADC in AI Chip Pipelines CIM analog arrays: ADC converts bitline current to digital MAC Radar / lidar: 10-16 bit ADC at 1-4 GS/s for IF digitization SerDes: 6-8 bit ADC in CTLE/DFE equalizer (56G+ PAM4) RF receiver: 12-16 bit direct-sampling ADC up to 3 GHz AI training monitor: precision ADC reads power rail voltage ADC = analog-digital boundary — every sensor path crosses it Speed-Resolution Trade-off Thermal noise floor: SNR_max = 6.02N + 1.76 dB (N = bits) Each extra bit = 2x precision = 4x capacitor area (kT/C noise) Doubling fs: loses ~1 ENOB to comparator metastability / jitter State-of-art (2025): 10 bit @ 5 GS/s, 1 mW — in 3 nm CMOS Time-interleaved ADC: N parallel ADCs at fs/N each → N x fs total Mismatch between interleaved channels adds spurs — calibration needed Process Scaling Impact Scaling benefits: smaller C → faster settling; lower Vdd → less power Scaling cost: lower Vdd → reduced dynamic range; more leakage Vt mismatch (sigma_Vt ~ A / sqrt(WL)) limits comparator accuracy SAR dominates <=7nm SoC ADC — lowest power, digital-friendly RF ADC (Analog Devices, TI, Xilinx RFSoC) at 28nm — cost vs perf Calibration BIST embedded in modern SoC ADC IP for post-silicon trim 5 GS/s @ 10 bit state-of-art SAR (3nm) 24 bit @ 192 kS/s sigma-delta audio ADC 6.02 dB / bit ideal SNR improvement kT/C noise floor fundamental resolution limit Walden FOM P/(2^ENOB · fs) in fJ/conv ADC sits at every analog-digital boundary: sensors, RF, power rails, CIM bitlines, SerDes CDRs — resolution and speed always trade off against power Analog Devices, Texas Instruments, and Xilinx (RFSoC) supply standalone ADCs; TSMC, Samsung, and Intel embed ADC IP in 5-3 nm SoC processes ``` **Flash ADCs** place 2^N comparators in parallel, each referenced to a different voltage tap on a resistor ladder. A single sample is converted in one clock cycle — making flash the fastest architecture, capable of multi-GS/s at 4-8 bit resolution. The cost is area and power that scale exponentially with bits: a 10-bit flash needs 1024 comparators. Flash ADCs appear in oscilloscopes, direct-sampling RF receivers, and the front end of pipeline ADCs. **Pipeline ADCs** chain a series of 1.5-bit stages, each resolving a coarse estimate and passing the residue to the next stage. Each stage operates on a different sample simultaneously (pipelined), enabling 10-14 bit resolution at 10-500 MS/s with moderate power. Pipeline ADCs are the workhorse for Wi-Fi receivers, cable modems, software-defined radio, and high-definition video capture. The latency through the pipeline is several clock cycles, which matters in closed-loop control applications. **SAR (successive approximation register) ADCs** perform a binary search: a capacitor DAC sets a test voltage at the midpoint, a comparator decides whether Vin is above or below, the result sets a bit and refines the estimate, and the process repeats N times for N bits. The result requires N comparisons instead of 2^N comparators, making SAR the most energy-efficient architecture per conversion. SAR ADCs achieve 8-18 bits at 1-100 MS/s and dominate portable, IoT, and biomedical applications. Modern SAR designs in 3 nm CMOS reach 10 bits at 5 GS/s at under 1 mW — an extraordinary figure of merit. **Sigma-delta ADCs** oversample the input at 256x or more using a 1-bit quantizer inside a feedback loop. The noise-shaping loop pushes quantization noise out of the baseband into high frequencies, where a decimation filter removes it. The result is 16-24 bit resolution at audio and precision measurement bandwidths. Sigma-delta ADCs are standard in audio codecs, precision weighing scales, and industrial sensor readout ICs. They trade bandwidth for dynamic range in a way no other architecture can match. **Key performance metrics** are ENOB (effective number of bits, derived from SNDR), SFDR (spurious-free dynamic range, the ratio of signal to the strongest harmonic), DNL/INL (differential and integral nonlinearity, errors in the code transition levels), and the Walden figure of merit (power divided by 2^ENOB times sample rate, in femtojoules per conversion). State-of-art SAR ADCs achieve below 1 fJ/conversion. **ADCs appear throughout AI chip systems.** CIM analog arrays require one ADC per bitline column to convert the analog MAC result to a digital partial sum. 77 GHz automotive radar digitizes IF signals at 1-4 GS/s with 10-14 bit resolution. 56G+ PAM4 SerDes embeds 6-8 bit ADCs in CTLE and DFE equalizers. Direct-RF sampling receivers (Xilinx RFSoC) place 12-14 bit, 2-5 GS/s ADCs in 16 nm CMOS to eliminate analog downconversion. Power management ICs embed 10-12 bit SAR ADCs for voltage rail monitoring in AI training systems. **Scaling effects cut both ways.** Smaller CMOS processes enable faster comparators and lower capacitance — beneficial for speed and power. But lower supply voltage reduces the analog dynamic range (signal headroom shrinks with Vdd), and threshold voltage mismatch (sigma_Vt proportional to A / sqrt(WL)) increases relative to the reduced signal swing, degrading comparator offset and DNL. Time-interleaved ADCs work around the speed limit by running N ADC slices in parallel at fs/N each, summing their outputs to achieve N times fs — but channel mismatch adds spurs that require background calibration.

Go deeper with CFSGPT

Get AI-powered deep-dives, save terms, and run advanced simulations — free account.

Create Free Account