sar adc design
**SAR ADC (Successive Approximation Register Analog-to-Digital Converter)** is the **most widely used ADC architecture that converts analog voltages to digital codes through a binary search algorithm** — offering the best combination of moderate speed (1-100 MSPS), medium-to-high resolution (8-18 bits), low power consumption, and compact area that makes it the default choice for SoC-embedded data conversion.
**How SAR ADC Works**
1. **Sample**: Track-and-hold circuit captures the input voltage (Vin).
2. **Compare MSB**: Internal DAC set to Vref/2. Comparator checks: Is Vin > Vref/2?
- Yes → MSB = 1, keep Vref/2. No → MSB = 0, remove Vref/2.
3. **Compare MSB-1**: DAC adds/subtracts Vref/4. Compare again.
4. **Repeat**: N comparisons for N-bit resolution.
5. **Output**: N-bit digital code after N clock cycles.
**Key Components**
| Component | Function | Critical Parameter |
|-----------|----------|-----------------|
| Capacitor DAC | Generates comparison voltages | Matching (< 0.1% for 10-bit) |
| Comparator | Compares Vin vs DAC output | Offset, noise, speed |
| SAR Logic | Binary search controller | Switching sequence |
| Sample/Hold | Captures input voltage | Bandwidth, settling |
**Capacitive DAC (CDAC)**
- Binary-weighted capacitor array: C, C/2, C/4, ... C/2^N.
- Charge redistribution: Switch capacitor plates between Vin, Vref, and GND.
- **Advantage**: Capacitors in CMOS are more linear and match better than resistors.
- **Bottom-plate sampling**: Reduces charge injection error.
**SAR ADC Advantages**
- **Low Power**: Only 1 comparator decision per bit per sample → minimal switching.
- Power scales with: $P \propto C_{total} \times V_{ref}^2 \times f_s$.
- State-of-art: < 10 fJ/conversion-step (Walden FOM).
- **Compact Area**: No op-amps needed (unlike pipeline ADC).
- **Scalable with CMOS**: Better performance at smaller nodes (smaller caps = less power).
**SAR ADC vs. Other Architectures**
| Architecture | Speed | Resolution | Power | Area |
|-------------|-------|-----------|-------|------|
| SAR | 1-100 MSPS | 8-18 bit | Very Low | Small |
| Pipeline | 100 MSPS-1 GSPS | 8-14 bit | Medium | Large |
| Flash | 1-10 GSPS | 4-8 bit | High | Very Large |
| Sigma-Delta | < 10 MSPS | 16-24 bit | Low | Medium |
**Advanced SAR Techniques**
- **Time-Interleaved SAR**: Multiple SAR channels sampling at offset times → aggregate bandwidth multiplied.
- **Noise-Shaping SAR**: Embed sigma-delta noise shaping in SAR loop → higher ENOB without oversampling penalty.
- **Redundant Bit SAR**: Extra comparison bits relax comparator speed requirements.
SAR ADC is **the workhorse data converter of the semiconductor industry** — its elegant binary search algorithm delivers the optimal power-resolution-speed tradeoff that has made it the most prevalent ADC architecture in modern SoCs, from IoT sensors to 5G transceivers.