sar adc design architecture

**SAR ADC Design** is **the architecture of successive approximation register analog-to-digital converters that perform binary search conversion using a capacitive DAC array and a single comparator to achieve 8-16 bit resolution at sampling rates from 1 MSPS to 500 MSPS with excellent power efficiency, making them the most widely used ADC topology in modern SoC designs**. **SAR ADC Operating Principle:** - **Binary Search Algorithm**: the SAR logic sequentially tests each bit from MSB to LSB by setting the bit, comparing the DAC output against the input, and keeping or clearing the bit based on the comparator decision—N bits require N comparison cycles - **Sample Phase**: input signal is sampled onto the bottom plate of the capacitive DAC array through a bootstrapped switch—track bandwidth must be >5x the input signal frequency for <0.5 LSB settling error - **Conversion Phase**: after sampling, the bottom plate switches connect to reference voltages (VREF+ or VREF-) based on SAR decisions—each switching event adds or subtracts a binary-weighted charge from the sampled charge - **Conversion Time**: total conversion time = N × comparator decision time + overhead—at 10-bit resolution with 500 ps comparator delay, conversion takes ~5 ns, enabling 100+ MSPS operation **Capacitive DAC Array Design:** - **Binary-Weighted Array**: capacitors sized in powers of 2 (C, 2C, 4C, ... 2^(N-1)×C) where the unit capacitance C is typically 1-10 fF—total capacitance of 2^N × C determines kT/C noise floor - **Split-Capacitor Architecture**: array partitioned into MSB and LSB sub-arrays connected through an attenuation capacitor—reduces total capacitance from 2^N×C to 2×2^(N/2)×C, saving area and power for resolutions >10 bits - **Capacitor Matching**: unit capacitor matching must be <0.1% (σ/C) for >10-bit linearity—achieved through common-centroid layout with dummy capacitors and unit cell sizing >5 μm × 5 μm in advanced nodes - **Switching Schemes**: monotonic switching reduces energy by 80% versus conventional switching—only the tested bit capacitor switches to VREF while previously decided bits remain connected, eliminating redundant charge redistribution **Comparator Design:** - **StrongARM Comparator**: dynamic latch comparator achieving sub-millivolt input-referred noise with zero static power—precharged and evaluated every SAR cycle - **Offset Calibration**: comparator offset of 5-20 mV in advanced nodes must be calibrated to <0.5 LSB—digital calibration using trim DAC or programmable capacitor array at comparator input - **Metastability and Speed**: comparator regeneration time constant τ determines probability of metastable output—cascaded regeneration stages reduce metastability BER to <10^-15 at target clock rates **Advanced SAR ADC Techniques:** - **Time-Interleaved SAR**: M parallel SAR channels operating with staggered sampling clocks achieve M× aggregate sampling rate—4-way interleaving of 250 MSPS SARs creates a 1 GSPS converter - **Noise-Shaping SAR**: integrating a residue amplifier or FIR filter into the SAR loop pushes quantization noise to higher frequencies—achieves 3-10 dB SNDR improvement without increasing DAC resolution - **Redundancy**: non-binary weighted DAC capacitors (e.g., 1.86× instead of 2×) provide bit-weight overlap that corrects comparator errors—enables faster comparator decisions by relaxing accuracy requirements **SAR ADC design dominates modern SoC analog integration because its digital-friendly architecture scales naturally with CMOS technology—smaller transistors enable faster comparators and smaller capacitors reduce power, achieving the remarkable figure of merit below 1 fJ/conversion-step that makes SAR ADCs the power efficiency champions of the data converter world.**