amba bus

**AMBA / AXI Bus** — ARM's standardized on-chip interconnect protocol family that defines how IP blocks (CPUs, GPUs, DMAs, peripherals) communicate inside an SoC. **AMBA Protocol Family** - **AXI (Advanced eXtensible Interface)**: High-performance, high-bandwidth. Used for CPU↔memory, GPU, DMA. Supports out-of-order transactions, burst transfers - **AHB (Advanced High-Performance Bus)**: Medium performance. Used for on-chip RAM, flash controllers. Simpler than AXI - **APB (Advanced Peripheral Bus)**: Low-bandwidth, low-power. Used for configuration registers, UART, SPI, I2C. Simple request-response **AXI Key Features** - **Separate read/write channels**: 5 channels (read address, read data, write address, write data, write response) - **Outstanding transactions**: Master can issue multiple requests without waiting for responses - **Burst transfers**: Transfer 1–256 beats in a single transaction - **Out-of-order completion**: Responses can return in different order from requests (tagged with ID) **Typical SoC Interconnect** ```svg ``` **AMBA is the de-facto standard** — virtually every ARM-based SoC (smartphones, IoT, automotive) uses AMBA protocols. Even non-ARM designs often adopt AXI for IP compatibility.