analog mixed signal cosimulation
**Analog-Mixed-Signal (AMS) Co-Simulation** is the **verification methodology that simultaneously simulates digital logic and analog circuits in a unified environment**, enabling verification of the critical interfaces between digital control logic and analog circuits — PLLs, ADCs, DACs, SerDes, voltage regulators, and sensor interfaces — where the majority of mixed-signal bugs reside.
Modern SoCs are fundamentally mixed-signal: even "digital" chips contain PLLs for clock generation, bandgap references for voltage regulation, I/O receivers with analog front-ends, and on-chip temperature sensors. Verifying these analog-digital interfaces requires co-simulation.
**Co-Simulation Approaches**:
| Approach | Analog Model | Speed | Accuracy | Use Case |
|----------|-------------|-------|----------|----------|
| **Full SPICE + Digital** | Transistor SPICE | Slowest (1x) | Highest | Final signoff |
| **FastSPICE + Digital** | Simplified transistor | 10-100x | High | Design iteration |
| **Real-number modeling (RNM)** | Behavioral (Verilog-AMS) | 1000x | Medium | Functional verification |
| **Wreal** | SystemVerilog real signals | 10000x | Medium-low | Architecture exploration |
| **Digital-only** | Ideal behavioral | Fastest | Low | Digital-focused verification |
**Real-Number Modeling (RNM)**: The practical sweet spot for most mixed-signal verification. Analog blocks are modeled as behavioral Verilog-AMS or SystemVerilog modules that process real-valued signals (voltages, currents) using mathematical equations rather than transistor-level simulation. An ADC model converts a real-valued input to a digital output with configurable resolution, INL/DNL, and conversion time — running 1000x faster than SPICE while capturing the functional behavior.
**Interface Verification Challenges**: The analog-digital boundary is where most bugs hide: **ADC verification** (does the digital controller handle all possible ADC output codes, including saturation and missing codes?); **PLL lock detection** (does digital logic correctly wait for PLL lock before using the generated clock?); **power supply sequencing** (does the digital reset deassert only after the analog regulator has stabilized?); **clock/data recovery** (does the digital CDR algorithm correctly track frequency drift in the analog front-end?).
**Methodology Flow**: Start with wreal/RNM models for architecture exploration and functional verification (80% of simulation cycles). Use FastSPICE co-simulation for critical interface timing verification. Use full SPICE only for final signoff of the most critical paths (PLL jitter, ADC linearity, SerDes eye diagram). This stratified approach balances simulation throughput with accuracy.
**Supply-Aware Simulation**: Advanced AMS verification includes supply network effects: how does digital switching noise on the power supply (SSO — simultaneous switching output) affect analog circuit performance? This requires coupling the digital simulator's activity-based power model with an analog supply network simulation — revealing noise coupling that pure digital or pure analog simulation would miss.
**AMS co-simulation bridges the analog-digital divide that represents the highest-risk interface in modern SoC design — analog bugs that escape to silicon are typically the most expensive to fix (requiring mask changes to analog layout), making thorough mixed-signal verification one of the highest-ROI verification investments.**