Antenna Effect

The antenna effect is damage a transistor suffers before the chip is ever finished, inflicted by the very process that is supposed to be building it. During plasma etch and other charged-process steps, a long, isolated metal wire connected to nothing but a transistor's gate acts exactly like a radio antenna: it collects stray charge from the plasma, that charge has nowhere to go but through the thin gate oxide beneath it, and the oxide can be degraded or punctured long before the chip is powered on for the first time.

The mechanism is pure physics of the process, not a flaw in the design's logic. A metal interconnect layer is built by depositing metal, then etching away everything that is not pattern, and both steps use a plasma — an ionized gas carrying net charge. A wire segment that is electrically floating at that point in the build, connected to nothing but a transistor gate on one end, has no path to ground except straight through the gate oxide. Since oxide is only a few nanometers thick and was never meant to carry current, even a modest accumulated charge produces a field strong enough to degrade it through Fowler-Nordheim tunneling, or in severe cases punch straight through.

The antenna ratio is the quantity design rule checking actually enforces, and it is a ratio, not a raw size. Risk is proportional to how much metal area is exposed to the plasma relative to how much gate area that metal ultimately connects to — a large wire feeding a large gate is comparatively safe, while the same wire feeding a small, sensitive gate concentrates all of that collected charge onto a tiny target. Foundries publish a maximum allowed ratio per metal layer in the process design kit, and an electrical rule check run alongside the geometric design rule check flags any net that exceeds it, well before tapeout.

Physical design has three real remedies, and each one trades a different resource to apply it. Adding a small protection diode at the gate gives accumulated charge a path to the substrate, but every diode costs die area and adds parasitic capacitance, so blanket application is expensive at scale. Splitting a long net across layers with a jumper — routing it up to a higher layer and back down — breaks the single continuous run before it accumulates a violating ratio, at the cost of extra vias and routing resources. The cheapest fix is structural: sequence the layout so the transistor's protective junction is connected before the offending metal layer is ever deposited, which needs no extra silicon at all but is only available where the process's own layer order permits it.

This is one of the few failure modes design rule checking must verify net by net rather than by local geometry alone. A standard design rule check looks at shapes in isolation — spacing, width, enclosure — and can be evaluated one polygon at a time. An antenna check instead has to trace each electrical net's full topology across every layer, sum the exposed metal area as it would exist at each intermediate fabrication step, and compare that running total against the connected gate area — a genuinely different kind of verification pass, run as an electrical rule check alongside, not inside, the geometric one.

The failure mode that makes this worth catching before tapeout is the quiet one, not the catastrophic one. A fully punctured gate oxide kills the transistor outright and gets caught at final test — expensive, but at least visible. Sub-catastrophic charging shifts threshold voltage and thins the oxide without killing the part immediately; it passes initial test and ships, then fails prematurely in the field under ordinary operating stress. That latent-defect risk, not the dead-on-arrival case, is the real argument for treating every antenna ratio violation as a sign-off blocker rather than a yield number to tolerate.

The antenna effect is the industry's standing reminder that a design file and a fabrication sequence are not the same object — a connection that is electrically correct in the finished schematic can still be electrically dangerous at an intermediate step that the schematic never shows. Catching it is why electrical rule checking exists as a discipline separate from geometric design rule checking, not a redundant pass over the same data.