Aperture Jitter

Aperture jitter is the error an analog-to-digital converter commits not by measuring the wrong voltage, but by measuring the right voltage at the wrong time. Every sample-and-hold circuit is supposed to capture the input at one precisely repeating instant per clock cycle; in reality that instant wanders by some small, random amount cycle to cycle, and for a signal that is changing at the moment of capture, a timing error translates directly into a voltage error.

The arithmetic is a straightforward first-order approximation: voltage error equals the signal's instantaneous slope times the timing error. For a sine wave of amplitude A and frequency f, the maximum slope occurs at the zero crossing and equals 2πfA; the resulting worst-case sampling error is therefore 2πfA·Δt_jitter, where Δt_jitter is the random timing deviation of that particular sample. This single relationship is why aperture jitter is fundamentally a high-frequency problem — the same absolute timing error that is harmless for a slowly changing DC-like signal becomes a large voltage error for a fast-changing one, because the slope the converter is trying to sample grows linearly with input frequency.

This is also why aperture jitter sets a hard frequency-dependent ceiling on achievable signal-to-noise ratio, independent of every other error source in the converter. Treating the jitter as a random process with rms value t_j, the resulting noise power translates into an SNR limit of roughly SNR = -20·log10(2π·f·t_j), expressed in decibels — a formula that depends only on input frequency and jitter, not on the converter's resolution, its reference voltage, or its quantization noise floor. A fourteen-bit converter sampling a high-frequency input can be entirely limited by a clock with a few hundred femtoseconds of jitter, in which case adding more resolution bits does nothing at all for the achievable SNR; the jitter floor, not the quantizer, is what actually bounds performance.

The practical consequence is that clock quality, not converter architecture, becomes the dominant design constraint for high-frequency sampling. A converter's own internal comparator noise and quantization floor set one ceiling; the sampling clock's jitter sets a separate, frequency-dependent ceiling, and whichever is lower wins. At low input frequency the quantization floor typically dominates and added jitter barely matters; past some crossover frequency the jitter term takes over completely, and improving the converter's internal circuitry buys nothing further. This is precisely why high-speed, high-resolution data converter systems spend disproportionate design effort on the clock distribution network — low-jitter clock generation, careful buffer selection, minimizing phase noise in any PLL in the clock path — treating clock quality as a first-order system specification on par with the converter itself, not a supporting detail.

Jitter itself splits into two distinct sources that demand different fixes, much like the injection-versus-feedthrough distinction covered elsewhere in this series. Random jitter is uncorrelated noise on the clock edge, typically dominated by thermal and flicker noise in the clock generation circuitry, and sets a noise-like SNR floor exactly as the formula above describes. Deterministic jitter, by contrast, is correlated with some other periodic signal — crosstalk from a neighboring clock, power-supply ripple coupling into the clock buffer, duty-cycle distortion — and shows up as discrete spurs in the output spectrum rather than a raised noise floor, which is a qualitatively different failure signature requiring supply isolation and layout fixes rather than a lower-noise clock source.

Aperture jitter is a reminder that an analog-to-digital converter is really measuring two things at once — voltage and time — and a converter can only ever be as good as the worse of its two measurements. Past the jitter crossover frequency, a sampling system's effective resolution is set entirely by its clock, and no improvement to the converter's own analog front end can buy back what an imprecise clock edge has already lost.