asic vs fpga
An ASIC and an FPGA solve the same problem — running a custom digital circuit — with opposite tradeoffs between speed and flexibility: an ASIC is a chip permanently hardwired at the foundry to do exactly one job extremely efficiently, while an FPGA is a chip whose internal wiring can be reprogrammed after manufacturing, trading some efficiency for the ability to change the circuit entirely without ever touching a fab again.
```flowchart
{
"rows": [
{ "type": "nodes", "items": [
{ "title": "Same starting point", "sub": "a digital circuit design (RTL)", "tone": "neutral" }
]},
{ "type": "arrow" },
{ "type": "group", "title": "Two ways to realize it in silicon", "items": [
{ "title": "ASIC route", "sub": "tape out to a foundry, permanently hardwired", "tone": "green" },
{ "title": "FPGA route", "sub": "program an off-the-shelf reconfigurable chip", "tone": "orange" }
]},
{ "type": "arrow" },
{ "type": "nodes", "items": [
{ "title": "ASIC: fastest, most efficient, fixed forever", "sub": "months of lead time, high NRE", "tone": "blue" },
{ "title": "FPGA: reprogrammable in minutes, less efficient", "sub": "available off the shelf immediately", "tone": "blue" }
]}
]
}
```
**An ASIC's efficiency comes directly from having nothing generic left in the design.** Every transistor and every wire on an ASIC exists because that specific circuit needs it — there is no leftover reconfigurable circuitry, no generic routing fabric, nothing serving a function the final product doesn't use. That specificity is exactly why an ASIC can be dramatically smaller, faster, and more power-efficient than any general-purpose alternative running the same function, at the cost of needing a full tapeout through a foundry, with its associated NRE cost and multi-month lead time, before a single unit exists.
```svg
```
**An FPGA trades peak efficiency for the ability to change the circuit entirely without new silicon.** Instead of hardwired connections, an FPGA is built from an array of generic logic blocks and a programmable routing fabric, and "programming" it means configuring which blocks connect to which — the equivalent of rewiring the chip's internals, but done electronically in minutes rather than through months of fabrication. That reconfigurability costs real efficiency: the same function typically runs slower and burns more power on an FPGA than on a purpose-built ASIC, because a meaningful fraction of the chip's area and power goes toward the generic routing fabric rather than the target function itself.
**The choice comes down to volume and how settled the design is, not which chip is "better."** An ASIC's high NRE cost only pays for itself at meaningful production volume, where its per-unit efficiency advantage compounds across millions of units; an FPGA makes sense for prototyping a design before committing to an ASIC, for low-volume or highly specialized products where the NRE would never be recovered, and for applications where the ability to update the hardware's logic in the field — after a bug fix or a changing standard — outweighs the efficiency cost.
| Aspect | ASIC | FPGA |
|---|---|---|
| Flexibility | None after tapeout — permanently fixed | Fully reconfigurable, even after deployment |
| Efficiency (speed, power, area) | Highest — nothing generic in the design | Lower — pays for generic, reconfigurable fabric |
| Upfront cost (NRE) | High — mask set, tapeout, verification | Low — buy an off-the-shelf part |
| Time to first working chip | Months (design through fabrication) | Immediate — program an existing chip |
| Best fit | High-volume, stable, performance-critical designs | Prototyping, low volume, designs that may change |
**Many real products use both, one after the other, rather than picking a single side permanently.** A design team commonly prototypes and validates a circuit on an FPGA first, catching logic errors cheaply and quickly before committing to an expensive, hard-to-reverse tapeout, and only moves that validated design to an ASIC once volume projections justify the NRE — treating the FPGA stage as a rehearsal for the ASIC rather than a permanent alternative to it.
Read ASIC versus FPGA through a volume-and-certainty lens: the question is never which chip is more advanced, it is whether the design is stable and produced at high enough volume to justify paying once, upfront, for silicon that does exactly one thing perfectly — or whether the ability to keep changing that circuit is worth giving up some of that efficiency.