assertion based verification
**Assertion-Based Verification (ABV)** is the **design verification methodology where designers embed executable temporal properties (assertions) directly in RTL code or bind them externally**, enabling continuous monitoring of design intent during simulation, formal analysis, and even in silicon through assertion synthesis — catching bugs at the earliest possible moment.
Assertions transform implicit design knowledge ("this FIFO should never overflow," "the acknowledge must come within 5 cycles of request") into explicit, machine-checkable properties that are verified on every simulation cycle.
**SystemVerilog Assertion (SVA) Types**:
| Type | Syntax | Use Case |
|------|--------|----------|
| **Immediate** | assert(condition) | Combinational checks |
| **Concurrent** | assert property(@(posedge clk) seq) | Temporal sequences |
| **Cover** | cover property(@(posedge clk) seq) | Functional coverage |
| **Assume** | assume property(@(posedge clk) seq) | Input constraints (formal) |
| **Restrict** | restrict property(@(posedge clk) seq) | Formal search space reduction |
**Temporal Operators**: SVA provides powerful temporal constructs: **|->** (overlapping implication — if antecedent matches, consequent must hold in the same cycle); **|=>** (non-overlapping implication — consequent starts next cycle); **##N** (delay N cycles); **[*N:M]** (repetition range); **$rose/$fell/$stable** (edge detection); **throughout** (condition holds during entire sequence); **within** (sequence completes within another); and **first_match** (stops at earliest match).
**Protocol Assertions**: The highest-value assertions verify bus protocol compliance: AXI assertions (RVALID must not assert without prior ARVALID, WSTRB must be consistent with AWSIZE, responses must match outstanding transactions), interrupt protocol (level must remain asserted until acknowledged), and memory controller protocol (read data must arrive within specified latency window after address phase).
**Formal Verification with Assertions**: Assertions serve dual duty in formal verification — **assert** properties are proven to hold for all possible input sequences (or counterexamples found), while **assume** properties constrain the input space to legal behavior. This bounded model checking can prove protocol compliance exhaustively within a given cycle depth, achieving verification completeness impossible with simulation.
**Assertion Coverage**: SVA **cover** directives track whether specific scenarios were exercised during simulation — filling the gap between code coverage (which lines executed) and functional coverage (which behaviors occurred). Uncovered assertions indicate missing test scenarios.
**Assertion Density Metrics**: Industry best practice targets 1 assertion per 10-20 lines of RTL code. High assertion density correlates with earlier bug detection and lower escape rates. Assertion libraries for standard protocols (AMBA, PCIe, USB) provide pre-verified property sets that dramatically accelerate verification closure.
**Assertion-based verification transforms design intent from documentation that nobody reads into executable specifications that run on every simulation cycle — making bugs self-reporting rather than requiring someone to notice incorrect waveform behavior, fundamentally shifting verification from passive observation to active monitoring.**