asynchronous design
**Asynchronous design** is the **digital design methodology that removes the global clock assumption and coordinates computation through local handshakes** - circuits proceed when data is ready, which can improve robustness to variation and electromagnetic noise.
**What Is Asynchronous Design?**
- **Definition**: Logic style where communication uses request-acknowledge protocols instead of fixed clock edges.
- **Core Elements**: Handshake channels, completion detection, and delay-insensitive coding styles.
- **Timing Model**: Correctness depends on protocol constraints rather than global skew budgets.
- **Use Cases**: Ultra-low-power systems, mixed-clock interfaces, and variation-tolerant control logic.
**Why It Matters**
- **Clock Distribution Relief**: Eliminates large clock-tree power and skew closure burden.
- **Variation Tolerance**: Local timing adapts naturally to process and voltage differences.
- **EMI Benefits**: Reduced periodic switching can lower spectral peaks.
- **Average-Case Speedup**: Blocks can complete faster than worst-case clock period when data paths are easy.
- **Heterogeneous Integration**: Facilitates communication across domains with different timing assumptions.
**How Teams Implement It**
- **Protocol Selection**: Choose bundled-data or delay-insensitive styles based on performance goals.
- **Verification Discipline**: Use formal and protocol-aware checks to validate deadlock freedom and correctness.
- **Physical Awareness**: Constrain interconnect delays and completion logic for robust silicon behavior.
Asynchronous design is **a powerful alternative to rigid clocked timing for specific high-variation and low-power problems** - when matched to the right subsystem, it can deliver strong resilience and efficiency advantages.