at-speed testing

**At-Speed Testing** is a **test methodology where the IC is tested at its actual operational clock frequency** — catching timing-related defects (delay faults, crosstalk) that slower-speed structural tests (stuck-at) would miss entirely. **What Is At-Speed Testing?** - **Definition**: Applying test patterns at the chip's target clock speed (e.g., 3 GHz). - **Methods**: - **Launch-on-Shift (LOS)**: Use the last shift clock edge to launch the transition. - **Launch-on-Capture (LOC)**: Use a fast capture clock to launch and capture the transition. - **Target**: Delay defects that only manifest at full operating frequency. **Why It Matters** - **Defect Coverage**: Small resistive shorts or weak transistors cause slight delays that only fail at speed. - **Reliability**: Marginal timing defects lead to field failures ("works in the lab, fails in the product"). - **Mandatory**: Most automotive and high-reliability standards (AEC-Q100) require at-speed testing. **At-Speed Testing** is **the sprint test for chips** — proving the silicon can perform under real-world speed pressure, not just walk through patterns slowly.