at speed testing atpg
**At-Speed Testing (ATPG)** is the **manufacturing test methodology that detects timing-related defects (transition delay faults, path delay faults) by launching a transition at the functional clock speed and capturing the result**, ensuring the chip operates correctly at its target frequency — catching defects that slower scan-shift-based stuck-at testing would miss.
Stuck-at testing verifies that each gate can produce both logic 0 and 1, but it doesn't verify timing. A defect that adds 100ps of delay to a critical path won't cause a stuck-at failure but will cause functional failure at speed. At-speed testing fills this gap.
**At-Speed Test Methods**:
| Method | Launch | Capture | Timing Control |
|--------|--------|---------|---------------|
| **Launch-Off-Shift (LOS)** | Last shift cycle | First capture clock | Shift clock → fast clock |
| **Launch-Off-Capture (LOC)** | First capture pulse | Second capture pulse | Two fast clock edges |
| **Broadside** | Same as LOC | Two functional-speed clocks | Preferred for timing accuracy |
**Launch-Off-Capture (LOC/Broadside)**: The dominant method. Two functional-speed clock pulses are applied: the first (launch) creates a transition at the fault site, the second (capture) samples the propagated result. The time between launch and capture equals one functional clock period. This directly tests whether signals propagate through combinational logic within the clock period.
**Launch-Off-Shift (LOS)**: The transition is created by the last scan shift operation, and a single functional-speed capture clock samples the result. Simpler to implement but the launch-to-capture timing depends on the scan shift clock-to-capture clock relationship, which may not match functional timing. Less preferred in modern flows.
**ATPG Considerations**: Transition fault ATPG generates two-pattern tests: V1 (initialization vector loaded via scan) and V2 (the transition-creating vector applied at speed). The ATPG tool must consider: **clock domain interactions** (multi-clock designs need careful launch/capture timing specification), **false paths** (don't test paths that never activate at functional speed), **power during test** (at-speed capture can cause 2-3x higher switching activity than functional operation, potentially causing IR drop failures that aren't real functional bugs).
**Test Power Management**: At-speed test vectors can toggle 30-50% of flip-flops simultaneously (versus 10-15% in functional operation). This causes excessive IR drop that may cause test failures unrelated to real defects. Mitigation: **power-aware ATPG** (constrain simultaneous switching), **multi-cycle capture** (reduce capture activity by testing fewer faults per pattern), and **supply voltage guardbanding** (test at slightly higher voltage to compensate for test-mode IR drop).
**Fault Coverage Targets**: Production-quality at-speed test achieves >95% transition fault coverage. Combined with >99% stuck-at coverage, this provides comprehensive defect detection. DPPM (defective parts per million) targets of <10 for automotive and <100 for consumer require both stuck-at and at-speed testing.
**At-speed testing is the critical complement to stuck-at testing in modern manufacturing — it catches the timing-dependent defects that increasingly dominate failure modes at advanced process nodes, where variability in transistor performance and interconnect delay makes speed-related defects more prevalent than static logic failures.**