scan test atpg
**Scan-Based Testing and ATPG** is the **Design-for-Test (DFT) methodology that replaces standard flip-flops with scan flip-flops (containing a scan MUX input) and connects them into shift registers (scan chains) — enabling an Automatic Test Pattern Generation (ATPG) tool to create test patterns that detect manufacturing defects in the combinational logic by shifting known patterns in, capturing the circuit response, and shifting results out for comparison against expected values**.
**Why Manufacturing Testing Is Essential**
A chip that passes all design verification (RTL simulation, formal verification, STA) can still fail due to manufacturing defects — metal bridging shorts, open vias, missing implants, gate oxide pinholes. These physical defects must be detected before the chip reaches the customer. Scan testing provides the controllability (set any internal node to a known value) and observability (read any internal node's response) needed to detect >99% of such defects.
**Scan Architecture**
1. **Scan Flip-Flop**: Each flip-flop has an additional multiplexed input (scan_in) controlled by a scan_enable signal. In normal mode, the flip-flop captures functional data. In scan mode, flip-flops form a shift chain — data shifts from scan_in to scan_out serially.
2. **Scan Chains**: All scan flip-flops on the chip are connected into ~100-10,000 chains (depending on test time budget). Chains are stitched during physical design to minimize routing overhead.
3. **Compression**: Test data compression (DFTMAX, XLBIST, TestKompress) wraps the scan chains with on-chip compression/decompression logic. A few external scan pins drive many internal chains simultaneously through a decompressor, and a compactor merges many chain outputs into a few external pins. Compression ratios of 50-200x reduce tester time and data volume by orders of magnitude.
**Fault Models and ATPG**
- **Stuck-At Fault (SAF)**: Models a net permanently stuck at 0 or 1. ATPG generates patterns that detect all detectable stuck-at faults. Target: >99% fault coverage.
- **Transition Fault (TF)**: Models a slow-to-rise or slow-to-fall defect. Requires at-speed pattern application (launch-on-shift or launch-on-capture) to detect timing-related defects. Coverage target: >97%.
- **Cell-Aware Faults**: ATPG uses transistor-level defect information within standard cells (opens, bridges between internal nodes) to generate patterns targeting intra-cell defects not covered by gate-level SAF/TF models. Improves DPPM (defective parts per million) escape rate.
**Test Metrics**
| Metric | Definition | Target |
|--------|-----------|--------|
| **Fault Coverage** | % of modeled faults detected | >99% (SAF), >97% (TF) |
| **Test Coverage** | % of testable faults detected | >98% |
| **ATPG Patterns** | Number of test patterns | 2,000-50,000 |
| **Test Time** | Time to apply all patterns on ATE | 0.5-5 seconds/die |
| **DPPM** | Defective parts shipped per million | <10 (automotive: <1) |
Scan-Based Testing is **the manufacturing quality firewall** — the systematic method that exercises every logic gate and wire on the chip with mathematically-generated test patterns, catching the physical defects that no amount of design simulation can predict.