scan chain basics

**Scan Chain / DFT (Design for Test)** — inserting test infrastructure into a chip so that manufacturing defects can be detected after fabrication. **How Scan Works** 1. Replace normal flip-flops with scan flip-flops (add MUX input) 2. Chain all scan flip-flops into shift registers (scan chains) 3. To test: Shift in a test pattern → switch to functional mode for one clock → capture result → shift out response 4. Compare response against expected values — mismatches indicate defects **Fault Models** - **Stuck-at**: A signal is permanently stuck at 0 or 1 - **Transition**: A signal is slow to switch (detects timing defects) - **Bridging**: Two signals are shorted together **Coverage** - Target: >98% stuck-at fault coverage for production testing - ATPG (Automatic Test Pattern Generation) tools create test patterns - More patterns = higher coverage but longer test time **Other DFT Features** - **BIST (Built-In Self-Test)**: On-chip test logic for memories and PLLs - **JTAG (IEEE 1149.1)**: Boundary scan for board-level testing - **Compression**: Compress scan data to reduce test time and pin count **DFT** adds 5-15% area overhead but is essential — without it, defective chips cannot be screened and would ship to customers.