scan chain insertion compression
**Scan Chain Insertion and Compression** is the **DFT (Design for Testability) methodology where sequential elements (flip-flops) are connected into shift-register chains to enable controllability and observability of internal state during manufacturing test**, combined with compression techniques that reduce test data volume and test time by 10-100x while maintaining fault coverage.
Manufacturing testing must detect stuck-at faults, transition faults, and other defects in every gate of the chip. Without scan, internal flip-flops are controllable and observable only through primary I/O — astronomically expensive in test vectors and time. Scan provides direct access to every sequential element.
**Scan Architecture**:
| Component | Function | Impact |
|-----------|---------|--------|
| **Scan flip-flop** | MUX-D FF (normal D input + scan input) | ~5-10% area overhead |
| **Scan chain** | Series connection of scan FFs | Serial shift-in/shift-out path |
| **Scan enable** | Selects between functional and scan mode | Global control signal |
| **Scan in/out** | Chain endpoints connected to chip I/O | Test access points |
**Scan Insertion Flow**: During synthesis, all flip-flops are replaced with scan-capable versions (mux-D or LSSD). The DFT tool then stitches flip-flops into chains: ordering considers physical proximity (to minimize routing congestion), clock domain partitioning (separate chains per clock domain), and power domain awareness (chains don't cross power domain boundaries that may be off during test).
**Test Compression**: Without compression, a design with 10M scan FFs and 100 chains requires 100K shift cycles per pattern and thousands of patterns — hours of test time at ATE (Automatic Test Equipment) costs of $0.01-0.10 per second. Compression architectures (Synopsys DFTMAX, Siemens Tessent, Cadence Modus) insert a decompressor at scan inputs and a compactor at scan outputs, feeding many internal chains from few external channels.
**Compression Details**: A 100x compression ratio means 100 internal scan chains are fed from 1 external scan input through a linear-feedback shift register (LFSR) based decompressor. The compactor (MISR or XOR network) compresses 100 chain outputs into 1 external scan output. ATPG (Automatic Test Pattern Generation) must be compression-aware — it knows which internal chain bits are dependent (due to shared decompressor seeds) and generates patterns that achieve high fault coverage within these constraints.
**Test Time and Cost**: Test time = (number_of_patterns × chain_length / compression_ratio) × shift_clock_period + capture_cycles. For a 10M-FF design with 100x compression: ~10K patterns, each shifting 1000 cycles at 100MHz = ~10ms per pattern = ~100 seconds total scan test. At-speed testing (running the capture at functional frequency) additionally tests for transition delay faults.
**Scan chain insertion and test compression represent the essential compromise between silicon testability and design overhead — the ~5-10% area cost of scan infrastructure pays for itself many times over by enabling the manufacturing test coverage that separates shipping products from engineering samples.**