scan test architecture

**Scan Test Architecture** is a **Design for Test (DFT) technique that transforms all flip-flops into scan flip-flops connected in chains** — enabling external test equipment to load and unload digital patterns to detect manufacturing defects. **Why Scan Testing?** - Post-manufacture test: Must verify every transistor, wire, and gate works correctly. - Without scan: Test sequence must propagate patterns through logic to observe outputs — millions of cycles needed for complete coverage. - With scan: Bypass logic entirely — directly load test patterns into all flip-flops in 1 cycle, apply test, observe results. **Scan Flip-Flop Architecture** - Standard FF: D input from functional logic, Q output to next stage. - Scan FF: Adds multiplexer at D input: - Functional mode: D = functional logic output. - Scan mode: D = SI (scan input) — serial chain. - Scan enable (SE) signal controls mode. **Scan Chain Operation** 1. **Shift-In**: Assert SE. Clock N cycles → shift test pattern serially into chain (one bit per FF per cycle). 2. **Capture**: De-assert SE. Apply one functional clock edge → circuit response captured into scan FFs. 3. **Shift-Out**: Assert SE. Clock N cycles → shift captured response out to scan output (SO). 4. Compare SO to expected response → PASS/FAIL. **Fault Coverage** - **Stuck-at-0 / Stuck-at-1**: Most common fault model. Node stuck at logic 0 or 1. - **Transition Fault**: Node fails to transition (slow-to-rise, slow-to-fall). - Coverage target: > 95% stuck-at, > 90% transition fault for production test. - ATPG (Automatic Test Pattern Generation) — EDA tools (Synopsys TetraMAX, Mentor FastScan) generate patterns targeting faults. **Scan Chain Compression** - N flip-flops → N cycles per pattern (slow). Problem: Millions of FFs in modern chips. - Scan compression: X-Core, EDT — compress 64 chains into 2 output pins → 32x test time reduction. - Industry standard: 100:1 or higher compression ratios. **JTAG (IEEE 1149.1)** - Boundary Scan: Scan chain around chip I/O boundary cells. - 4-wire TAP (Test Access Port): TDI, TDO, TCK, TMS. - Tests PCB-level connectivity: Can detect opens, shorts between ICs on PCB. Scan architecture is **the backbone of production IC test** — without scan, comprehensive manufacturing test would be economically infeasible for the billions of gates in modern SoCs, making DFT insertion during design an absolute requirement for yield learning and quality assurance.