jtag boundary scan
**JTAG (IEEE 1149.1 Boundary Scan)** is the **standardized test access port and scan architecture that provides a serial interface for testing interconnections between chips on a PCB, accessing on-chip debug features, and programming flash/FPGA devices** — using a simple 4-5 wire interface (TCK, TMS, TDI, TDO, optional TRST) to shift data through boundary scan cells at every I/O pin, enabling board-level manufacturing test without physical probe access and serving as the universal debug interface for embedded systems development.
**JTAG Signals**
| Signal | Direction | Purpose |
|--------|-----------|--------|
| TCK | Input | Test Clock — serial clock for all JTAG operations |
| TMS | Input | Test Mode Select — controls TAP state machine |
| TDI | Input | Test Data In — serial data input to scan chain |
| TDO | Output | Test Data Out — serial data output from scan chain |
| TRST* | Input | Test Reset — optional async reset of TAP controller |
**TAP Controller State Machine**
- 16-state FSM controlled by TMS signal on TCK rising edges.
- Key states:
- **Test-Logic-Reset**: All test logic disabled, chip operates normally.
- **Shift-DR**: Shift data through selected data register (boundary scan, IDCODE, etc.).
- **Shift-IR**: Shift instruction into instruction register.
- **Update-DR/IR**: Latch shifted data into parallel output.
- **Capture-DR**: Sample current pin/register values into shift register.
**Boundary Scan Architecture**
```
TDI → [BS Cell Pin1] → [BS Cell Pin2] → ... → [BS Cell PinN] → TDO
| | |
[I/O Pad] [I/O Pad] [I/O Pad]
| | |
[To PCB trace] [To PCB trace] [To PCB trace]
```
- Each I/O pin has a boundary scan cell with:
- **Capture**: Sample actual pin value.
- **Shift**: Pass data from TDI to TDO through chain.
- **Update**: Drive captured/shifted value onto pin.
**Standard JTAG Instructions**
| Instruction | Function |
|-------------|----------|
| BYPASS | 1-bit path from TDI to TDO → skip this chip in chain |
| EXTEST | Drive values from boundary scan cells onto pins → test board traces |
| SAMPLE/PRELOAD | Capture pin states without affecting operation |
| IDCODE | Read 32-bit device identification register |
| INTEST | Apply test vectors to chip core through boundary scan |
**Board-Level Testing with JTAG**
1. **Open detection**: Drive value on chip A output → read on chip B input via boundary scan.
2. **Short detection**: Drive different values on adjacent nets → detect conflicts.
3. **Stuck-at**: Force known values → verify they propagate correctly.
- Coverage: Tests 95%+ of solder joint defects without bed-of-nails fixture.
**Debug Extensions**
- **ARM CoreSight**: Debug access port (DAP) over JTAG → halt CPU, read/write memory, set breakpoints.
- **RISC-V Debug Module**: JTAG-accessible debug interface per RISC-V debug spec.
- **FPGA programming**: Xilinx/Intel program bitstreams through JTAG.
- **IEEE 1149.7**: Reduced pin JTAG — 2 pins (TCK, TMSC) instead of 4-5 → saves package pins.
**JTAG Chain (Multi-Chip)**
- Multiple chips daisy-chained: TDO of chip 1 → TDI of chip 2 → ... → TDO of chip N.
- All share TCK and TMS → all TAP controllers move in sync.
- BYPASS instruction: Non-targeted chips pass data through 1-bit register → minimize chain length.
JTAG boundary scan is **the universal test and debug interface of the electronics industry** — its standardization across virtually every digital IC manufactured since the 1990s provides a guaranteed access mechanism for board test, chip debug, and device programming that remains indispensable even as chips grow more complex, making JTAG support a non-negotiable requirement in every chip's I/O ring design.