boundary scan
**Boundary Scan (JTAG / IEEE 1149.1)** is the **standardized on-chip test interface that enables testing of chip interconnects, board-level connections, and chip programming through a simple 4-wire serial protocol** — providing controllability and observability of every chip I/O pin without physical probe access, essential for testing dense BGA packages where pins are hidden under the chip.
**JTAG Interface (4 Wires)**
| Signal | Direction | Function |
|--------|-----------|----------|
| TCK | Input | Test Clock — serial shift clock |
| TMS | Input | Test Mode Select — controls TAP state machine |
| TDI | Input | Test Data In — serial data input |
| TDO | Output | Test Data Out — serial data output |
| TRST (optional) | Input | Test Reset — async reset of TAP controller |
**TAP Controller (Test Access Port)**
- 16-state FSM that sequences test operations.
- Key states: Shift-DR (shift data through registers), Shift-IR (select instruction), Update-DR (apply data).
- Controlled entirely by TMS signal — same state machine in every JTAG-compliant chip.
**Boundary Scan Operation**
1. **Boundary Scan Register**: A shift register cell at every I/O pin of the chip.
2. **EXTEST Instruction**: Boundary cells drive and capture pin values — tests board-level solder joints.
3. **SAMPLE Instruction**: Captures functional pin values without interrupting chip operation.
4. **BYPASS Instruction**: 1-bit bypass register shortens the scan chain for faster access to other chips on the chain.
**Board-Level Testing**
- Multiple JTAG chips daisy-chained: TDO of Chip 1 → TDI of Chip 2 → ... → TDO to board tester.
- Tester drives patterns through the chain → detect open solder joints, shorts, missing components.
- **Critical for BGA**: 1000+ pin BGA packages have solder balls hidden under the chip — no probe access possible.
**Beyond Testing — JTAG Applications**
- **FPGA Programming**: JTAG is the standard interface for loading bitstreams into FPGAs.
- **Flash Programming**: Program on-board SPI flash through JTAG boundary scan.
- **Debug**: ARM CoreSight, RISC-V debug module — all use JTAG as the transport layer.
- **IEEE 1149.6**: Extension for AC-coupled (differential) signals like LVDS, SerDes.
- **IEEE 1687 (IJTAG)**: Internal JTAG — access to on-chip instruments (MBIST, thermal sensors, PLL tuning).
Boundary scan is **one of the most universally adopted standards in electronics** — virtually every digital IC manufactured since the 1990s includes a JTAG interface, making it the lingua franca of chip testing, board testing, programming, and debug.