scan

**Scan Chain Insertion and Design for Testability (DFT)** is **the inclusion of test infrastructure enabling external observation and control of internal chip signals — allowing comprehensive manufacturing test and reducing test generation burden**. Scan chains are fundamental testability structures converting internal sequential logic into externally-controllable/observable elements. Standard multiplexer-based scan inserts a 2:1 mux before each flip-flop data input. Mux selects between functional (normal operation) and scan (test mode) inputs. Serial scan chain connects flip-flops, enabling shift operations to load/unload test vectors. Scan pins: scan_in (test data in), scan_out (test data out), scan_enable (mode control), clock (timing). Test procedure: shift in test vectors, pulse clock to capture response, shift out response, compare to expected. Scan insertion automation: design tools insert multiplexers and construct chains. Scan compression: full chip scan becomes impractical for large designs (billions of flip-flops). Scan compression groups flip-flops into multiple scan chains. Multiple chains reduce shift time. Compression further groups chains into logical units. Decompression logic expands pseudo-random test patterns into full scan vectors. Compression reduces tester cost and test time. Partial scan: selective scan of critical flip-flops reduces overhead. Reduced-scan methodologies identify flip-flops necessary for test coverage. Scan clock management: scan and functional clocks may differ. Scan operates at slower rate than functional clocks. Overlapping clocks cause issues — careful gating prevents violations. Latch-up risks during scan (high-energy states) require design consideration. Scan test length: number of clock cycles to shift in/out determines total test time. Large designs require thousands of cycles. Test compression and parallel scan minimize test time. Memory test: embedded memories (SRAM, Flash) require special test logic. Built-in self-test (BIST) generates test patterns internally. SRAM BIST tests address and data paths. Flash BIST tests programming, erase, and read. Memory compiler provides test structures. Boundary scan (IEEE 1149.1 JTAG): separate test standard enabling chip-to-chip communication for system-level test. Chain of scan cells at chip I/O. Inter-chip connections enable test propagation. Legacy DFT methodology with scan dominates. Newer approaches (LBIST, MBIST) complement or replace scan. Side-channel risks: scan exposes internal signals — secure applications require scan disable in deployment. Test infrastructure area: scan multiplexers and chains add area (typically 5-15%). Power: scan shift power exceeds functional power due to high switching. Thermal management during test is important. **Scan chain insertion provides comprehensive manufacturing testability, enabling detection of defects and faults through structured shift and capture operations, though adding area and power overhead.**