design for testability dft

**Design for Testability (DFT)** is the **set of design techniques that add hardware structures to a chip — scan chains, BIST (Built-In Self-Test) engines, compression logic, and test access ports — specifically to enable manufacturing defect detection after fabrication, where achieving >99% stuck-at fault coverage and >90% transition fault coverage is required for commercial viability because shipping defective chips costs 10-100x more than detecting them during wafer test and package test**. **The Testing Problem** A modern SoC contains billions of transistors, any of which can be defective. Without DFT, testing would require applying patterns to primary inputs and observing primary outputs — but internal logic is deeply buried, making it impossible to control and observe enough internal state to detect defects. DFT adds controllability (ability to set internal nodes) and observability (ability to read internal nodes). **Scan Chain Architecture** The foundational DFT technique: every flip-flop in the design is replaced with a scan flip-flop that has a multiplexed input — in normal mode it captures functional data, in scan mode it forms a shift register. All scan flip-flops are stitched into chains. - **Scan Shift**: Test patterns are serially shifted into all scan chains simultaneously (parallel chain loading). - **Capture**: One or more functional clock pulses apply the pattern and capture the response into scan flip-flops. - **Scan Out**: Responses are shifted out while the next pattern is shifted in (overlapped scan). **ATPG (Automatic Test Pattern Generation)** EDA tools (Synopsys TetraMAX, Cadence Modus) algorithmically generate input patterns that detect specific fault types: - **Stuck-At Faults**: Each net stuck at 0 or stuck at 1. The classical fault model. Target: >99.5% coverage. - **Transition Faults**: Each net slow-to-rise or slow-to-fall. Detects timing-related defects. Target: >95% coverage. - **Path Delay Faults**: Specific paths slower than specification. Used for at-speed test validation. **Test Compression** Modern SoCs have 100M+ scan cells. Without compression, patterns require hours of test time on ATE. Compression logic (Synopsys DFTMAX, Cadence Modus) reduces test data volume by 50-200x using on-chip decompressors (input) and compactors (output), reducing ATE time from hours to minutes. **BIST** - **Logic BIST (LBIST)**: On-chip pseudo-random pattern generator (PRPG) and multiple-input signature register (MISR) test combinational logic without ATE. - **Memory BIST (MBIST)**: Dedicated controller runs march algorithms (March C-, March LR) on each SRAM, testing every cell for stuck-at, coupling, and retention faults. **Design for Testability is the economic enabler of semiconductor manufacturing** — the engineering discipline that ensures defective chips are caught before they reach customers, protecting both the manufacturer's yield economics and the end product's field reliability.