scan chain atpg design

**Scan Chain Design and ATPG** is the **design-for-testability (DFT) methodology that converts sequential circuit elements (flip-flops) into scannable elements connected in shift-register chains — enabling automatic test pattern generation (ATPG) tools to generate test vectors that detect manufacturing defects (stuck-at, transition, bridging faults) with >99% coverage, making it possible to distinguish good chips from defective ones at production test with tests that run in seconds rather than the hours that functional testing would require**. **Why Scan-Based Testing** A sequential circuit with N flip-flops has 2^N internal states. Testing all state transitions functionally is intractable for even modest N. Scan design converts the sequential testing problem into a combinational one: load any desired state via scan shift, apply one clock (capture), and shift out the result. ATPG tools generate patterns for the combinational logic between scan stages. **Scan Architecture** - **Scan Flip-Flop**: A multiplexed flip-flop with two inputs — functional data input (D) and scan input (SI). A scan enable (SE) signal selects between normal operation and scan mode. In scan mode, flip-flops form a shift register (scan chain). - **Scan Chain Formation**: All scannable flip-flops are stitched into one or more chains. Scan-in port → FF1 → FF2 → ... → FFn → Scan-out port. A chip with 10M flip-flops might have 100-1000 scan chains of 10K-100K elements each. - **Scan Test Procedure**: (1) SE=1: Shift test pattern into scan chains via scan-in ports (shift cycles = chain length). (2) SE=0: Apply one functional clock (launch/capture for transition faults). (3) SE=1: Shift out captured response via scan-out ports. (4) Compare response to expected values. **ATPG (Automatic Test Pattern Generation)** ATPG tools algorithmically generate input patterns and expected outputs: - **Stuck-At Fault Model**: Each net is assumed stuck at 0 or 1. ATPG must sensitize the fault (create a difference between faulty and fault-free behavior) and propagate it to an observable output (scan-out). D-algorithm, PODEM, FAN are classic ATPG algorithms. - **Transition Fault Model**: Tests timing-dependent defects — the circuit must transition (0→1 or 1→0) at the fault site within one clock period. Requires launch-on-shift (LOS) or launch-on-capture (LOC) test modes. - **Pattern Count**: Typical: 1,000-10,000 patterns for >99% stuck-at coverage. 5,000-50,000 patterns for >95% transition coverage. **Scan Compression** Shifting 10M flip-flops through 1000 chains at 100 MHz takes 100 μs per pattern × 10,000 patterns = 1 second. For millions of chips, test time directly impacts cost. Compression reduces this: - **Compressor/Decompressor**: On-chip decompressor expands a small number of external scan inputs into many internal scan chain inputs. On-chip compressor reduces many scan-out chains to a small number of external outputs. Compression ratio: 10-100×. - **Synopsys DFTMAX, Cadence Modus**: Commercial scan compression tools achieving 50-200× compression while maintaining fault coverage. Test data volume and test time reduced proportionally. **Test Quality Metrics** - **Stuck-At Coverage**: >99.5% required for production quality. 99.9%+ for automotive (ISO 26262 ASIL-D). - **Transition Coverage**: >95% for high-reliability applications. - **DPPM (Defective Parts Per Million)**: The ultimate metric — test escapes that reach the customer. Target: <10 DPPM for consumer, <1 DPPM for automotive. Scan Chain Design and ATPG is **the testability infrastructure that makes billion-transistor manufacturing economically viable** — the DFT methodology that transforms the intractable problem of testing combinational and sequential logic into a systematic, automated process achieving near-complete defect coverage in seconds of test time.