testability scan chain

**Design for Testability (DFT)** is the **set of design techniques and hardware structures (scan chains, BIST, JTAG) inserted into a chip to make it manufacturing-testable — enabling automatic test pattern generation (ATPG) tools to detect fabrication defects (stuck-at faults, transition faults, bridging faults) with 95-99% fault coverage, where the DFT overhead of 5-15% area increase is vastly outweighed by the ability to screen defective parts before they reach customers**. **Why DFT Is Necessary** A 10-billion-transistor chip has ~30 billion potential stuck-at fault sites. Without DFT, testing requires applying functional patterns that exercise each internal node — computationally intractable for modern designs. DFT structures convert the chip into a testable structure by providing controllability (ability to set internal nodes to desired values) and observability (ability to read internal node states). **Scan Design** The fundamental DFT technique: - Every flip-flop (register) is replaced with a scan flip-flop that has an additional multiplexed input. - In **scan mode**, all flip-flops are chained into shift registers (scan chains). Test patterns are shifted in serially, the circuit is clocked for one functional cycle (capture), and results are shifted out for comparison. - **Trade-offs**: Scan insertion adds a mux per flip-flop (~5% area), increases routing for scan chains, and adds 2 pins (scan-in, scan-out per chain). Compression (DFTMAX, TestKompress) reduces the number of external scan pins by 10-100x using on-chip decompressor/compressor logic. **Automatic Test Pattern Generation (ATPG)** - ATPG tools (Synopsys TetraMAX, Cadence Modus) automatically generate test patterns that detect each target fault. - **Stuck-At Faults**: Node permanently at logic 0 or 1. The simplest fault model — one pattern per fault. - **Transition Faults**: Node cannot transition fast enough (delay defect). Requires a two-pattern sequence: initialization pattern + launch pattern. - **Cell-Aware ATPG**: Uses transistor-level fault models within standard cells to detect intra-cell defects not covered by gate-level fault models. Achieves 99%+ defect coverage. **BIST (Built-In Self-Test)** - **Memory BIST (MBIST)**: On-chip state machine generates March test patterns for embedded SRAMs. Tests every bitcell and peripheral circuit without external equipment. Essential because SRAMs are too large for scan-based testing. - **Logic BIST (LBIST)**: Pseudo-random pattern generator (LFSR) drives scan chains, and an output signature register (MISR) compresses responses. Self-contained testing without external tester — used for in-system testing and burn-in. **JTAG (Boundary Scan)** IEEE 1149.1 standard. A serial interface (TCK, TMS, TDI, TDO) provides access to boundary scan cells at every chip I/O pin. Enables board-level interconnect testing (checking solder joints) and chip-level debug access without physical probing. DFT is **the manufacturing quality infrastructure embedded in every chip** — the hidden hardware that enables billion-transistor devices to be tested in seconds rather than years, ensuring that defective parts are caught at the factory instead of failing in the field.