Automatic Defect Classification (ADC)

Automatic defect classification exists because an inspection tool can find thousands of candidate defect sites on a single wafer far faster than any engineer could ever look at each one, but finding a defect and knowing what it is are two very different problems, and only the second one tells a process team what to fix. ADC closes that gap by running captured defect images, whether from an optical inspection tool or a review SEM, through an image-processing or machine-learning classifier that sorts each detected site into a defect class such as particle, scratch, pit, pattern defect, residue, or bridge, without requiring a human to manually review every single image. That automated binning step is what turns a raw defect count into an actionable, class-resolved signal that a fab can trace back to a specific tool, chamber, or process step.

An ADC classifier assigns each captured defect image to a predefined class using either a rule-based feature classifier or a trained convolutional neural network, and the choice between the two shapes both accuracy and maintenance burden. A rule-based classifier extracts hand-engineered features such as size, aspect ratio, and gray-level contrast and applies threshold logic tuned by an engineer, while a CNN-based classifier learns its own feature representation directly from a labeled training image set, typically requiring several thousand labeled review images per defect class before classification accuracy stabilizes. Image resolution below 100 nm is generally needed to reliably distinguish a fine pattern defect from a similarly sized particle, since coarser imaging blurs exactly the shape and edge detail the classifier depends on. A classifier with a confidence score below a set threshold, often around 70%, routes the image to human review rather than committing to an automated call, trading some throughput for accuracy on the hardest cases.

Classification accuracy and purity are the two metrics that actually matter in production, and neither one alone tells the full story of how well an ADC recipe is performing. Accuracy measures how often the classifier's call agrees with a human expert's ground-truth label, while purity measures what fraction of the defects sorted into a given bin genuinely belong there, and a recipe can hold high overall accuracy while still returning a badly impure bin for one specific, harder-to-distinguish class. A mature ADC recipe commonly holds accuracy in the 85% to 95% range across the full defect population, though any single class, particularly a rare one with few labeled training examples, can sit well below that average. Particle-versus-residue confusion is consistently the most common error pair across fabs, since both classes can present as a roughly round, moderate-contrast blob at typical inspection resolution, and separating them reliably often takes additional context such as location relative to pattern features rather than shape alone.

Defect binning feeds directly into a Pareto chart, and it is that Pareto, not the raw defect count, that tells an engineering team where to spend limited investigation time. Ranking defect classes by count on a given lot typically shows the top three classes accounting for 70% to 80% of the total defect population, so a team chasing yield improvement gets the most leverage by attacking the leading Pareto bar rather than spreading effort evenly across every class. A sudden change in Pareto rank order, such as a normally minor bridge-defect class jumping to the top position, is itself a strong excursion signal, often more sensitive than a simple total-defect-count trend because it points directly at which process module likely changed. Pareto data accumulated across many lots also builds the historical baseline against which a single lot's classification result is judged, turning one ADC run into a data point in a much longer yield-learning trend.

ADC accuracy degrades over time as process conditions drift away from the conditions the classifier was originally trained on, which is why a retraining and monitoring loop has to run alongside the classifier itself. A classifier trained on one layer or one tool set can lose several percentage points of accuracy when applied unchanged to a new layer with different pattern density or a new inspection tool with different imaging characteristics, and that drift is rarely obvious until purity metrics are tracked explicitly against a rolling baseline. Retraining is typically triggered once measured purity for any class drifts more than 10% below its qualified target, at which point new labeled images are collected and the classifier is refreshed rather than left to silently degrade. Image-resolution limitations compound this problem directly, since a classifier cannot distinguish two defect classes that look identical at the inspection tool's native pixel size regardless of how much training data it receives. Fabs running a mixed inspection fleet, including tools comparable to Semilab defect and metrology platforms, often maintain a separate trained classifier per tool type rather than one shared model, since even small differences in illumination geometry or detector response between platforms can shift the feature space enough to degrade cross-tool accuracy by several percentage points.

Integrating ADC output with the inspection tool's sampling plan and the fab's excursion-detection system turns a per-lot classification result into a real-time process-control signal rather than an offline engineering report. A typical inline recipe samples a subset of die across the wafer, often between 10% and 30% of total die area, rather than inspecting every site at full density, trading some detection completeness for a throughput that keeps pace with the production line. When a specific defect class exceeds a control limit, commonly set at two to three times its rolling baseline count, an automated excursion alarm can hold the affected lot before it advances to the next process step, cutting the delay between a tool going out of control and an engineer finding out about it from potentially several process steps down to essentially the same shift. Excursion thresholds are periodically re-tuned as the underlying process matures, since a control limit set during early ramp is almost always too loose once yield stabilizes and defect counts fall by 50% or more from ramp-era levels.

Ambiguous or high-value ADC calls are routinely confirmed by physical failure analysis rather than trusted on classification confidence alone, closing the loop between an automated bin and a verified root cause. AFM topography resolves surface height differences as small as a few nm, distinguishing a true pit from a shallow residue patch that can look similar in a plan-view inspection image. SIMS depth profiling and XPS surface analysis identify the chemical composition of a residue or contamination-class defect, confirming whether it traces back to a specific chemistry used in an upstream process step. DLTS spectroscopy is occasionally added when a pattern defect is suspected of introducing an electrically active trap level, tying a purely visual classification back to a measurable device-level consequence. Reserving this confirmatory analysis for the highest-Pareto-rank or lowest-confidence calls keeps the physical analysis workload manageable while still catching the classification errors that would otherwise mislead a yield-learning decision. Some fabs go a step further and correlate a pattern-defect bin against electrical parametric data pulled from a four-point probe sheet-resistance scan on the same lot, since a defect class that consistently tracks a resistivity or continuity anomaly is far more likely to be yield-relevant than one that shows no electrical correlation at all, and that correlation itself can be used to re-rank which ADC class deserves the next engineering investigation.

Inspection tool captures candidate defect images → Preprocess and crop defect region of interest → ADC classifier assigns defect class → Low-confidence calls routed to human review → Classified defects binned by class → Build defect Pareto for the lot → Compare Pareto rank against rolling baseline → Route flagged classes to AFM, SIMS, XPS, or DLTS confirmation and yield learning

Viewed through a defect-classification yield engineering lens, automatic defect classification earns its place in the inline flow because it converts an overwhelming volume of raw inspection images into a small number of ranked, actionable defect classes, giving a fab the specific, class-resolved signal it needs to trace a yield-limiting excursion back to its process origin far faster than manual review ever could.