backside power delivery bspdn

**Backside Power Delivery Network (BSPDN)** is the **revolutionary chip architecture that moves the power supply wiring from the front side (where it competes with signal routing) to the back side of the silicon wafer — delivering power through the wafer substrate via nano-TSVs directly to the transistors, freeing up 20-30% of front-side metal routing resources for signals, reducing IR drop, and enabling the next generation of density and performance scaling beyond what front-side-only interconnect architectures can achieve**. **The Power Delivery Problem** In conventional chips, power supply wires (VDD, VSS) share the same metal interconnect layers as signal wires. At advanced nodes: - Power wires consume 20-30% of the metal tracks in lower layers (M1-M3), reducing signal routing capacity and increasing cell height. - Current flows through 10+ metal layers from top-level power pads to transistors, creating significant IR drop (voltage droop) and EM (electromigration) risk in narrow wires. - Power delivery grid design is a major constraint on standard cell architecture and logic density. **BSPDN Architecture** 1. **Front Side**: After complete FEOL + BEOL fabrication on the front side, the wafer is bonded face-down to a carrier wafer. 2. **Wafer Thinning**: The original substrate is thinned from the back side to ~500 nm - few μm thickness (below the transistor active layer). 3. **Nano-TSV Formation**: Through-Silicon Vias (~50-200 nm diameter) are etched from the back side through the thinned substrate, landing on the buried power rails (BPR) at the transistor level. 4. **Backside Metal Layers**: 1-3 metal layers are fabricated on the back side, forming a dedicated power distribution network connected through the nano-TSVs. 5. **Backside Bumps**: Power supply bumps (C4 or micro-bumps) connect the backside power network to the package. **Key Benefits** - **Signal Routing Relief**: Removing power wires from front-side M1-M3 frees 20-30% of routing tracks for signals, enabling smaller standard cells (reduced cell height from 6-track to 5-track or 4.5-track) and higher logic density. - **Reduced IR Drop**: Power current flows through dedicated thick backside metals and short nano-TSVs directly to transistors, instead of through 10+ thin signal-optimized metal layers. IR drop reduction of 30-50%. - **Improved EM**: Dedicated power metals can be thicker and wider than front-side signal metals, carrying higher current without EM risk. - **Thermal Benefits**: Backside metal layers provide additional heat spreading paths. **Challenges** - **Wafer Thinning**: Thinning to <1 μm without damaging the transistor layer. Wafer handling and mechanical integrity during subsequent backside processing. - **Nano-TSV Alignment**: Aligning backside features to front-side buried power rails through a thinned substrate. Overlay targets must be visible from the back side (infrared alignment through silicon). - **Process Complexity**: Essentially doubles the number of metallization steps. Front-side BEOL + wafer bonding + thinning + backside BEOL adds significant cost and cycle time. **Industry Adoption** - **Intel**: PowerVia technology demonstrated at Intel 4 process; production at Intel 18A (1.8 nm equivalent) and beyond. - **TSMC**: BSPDN planned for N2P (2nm enhanced) and A14 (1.4 nm) nodes. - **Samsung**: Backside power delivery roadmap for 2nm/1.4nm GAA nodes. BSPDN is **the architectural revolution that rethinks 50 years of chip wiring convention** — by separating power and signal into different sides of the die, unlocking the density and performance improvements that front-side-only interconnect scaling can no longer deliver.