semiconductor backside power delivery

**Backside Power Delivery Network (BSPDN)** is the **advanced semiconductor architecture that routes power supply lines (VDD and VSS) through the back of the silicon wafer rather than through the front-side metal interconnect stack — freeing the front-side metals exclusively for signal routing, reducing IR drop by 30-50%, enabling 10-15% logic density improvement, and fundamentally changing the chip design paradigm introduced at Intel's 20A/18A nodes and planned for TSMC's N2 process**. **The Problem with Frontside Power** In conventional designs, power and signal wires share the same metal stack above the transistors. Power rails consume 20-30% of the metal routing resources on the lower metal layers (M0-M3), creating congestion that limits cell height scaling. As transistor density increases, more power must be delivered through narrower wires, increasing IR drop (voltage loss across the resistance of the power network) — at advanced nodes, IR drop budgets consume 5-10% of the supply voltage. **How BSPDN Works** 1. **Transistor Fabrication**: Standard FEOL processing builds transistors on the wafer front side. 2. **Frontside Metallization**: Only signal routing layers are built on the front side — no power rails in lower metals. This opens up routing channels for signals. 3. **Wafer Thinning**: The wafer is bonded face-down to a carrier wafer, and the original substrate is thinned from ~775 μm to ~1 μm, exposing the bottom of the transistor source/drain regions. 4. **Backside Processing**: Nano-TSVs (Through-Silicon Vias) are etched from the exposed backside to connect to the transistor source/drain contacts. Backside metal layers (power rails) are fabricated. 5. **Power Delivery**: Wide, thick backside metal lines deliver VDD and VSS directly to transistors through nano-TSVs. The short, direct path from backside power to transistor minimizes IR drop. **Buried Power Rails (BPR)** A related but earlier technology: power rails are embedded below the transistor level (in the silicon substrate, beneath the active devices) rather than above. BPR is the stepping stone toward full BSPDN — it moves power rails off the signal metal layers but still delivers power from the front side through taller, deeper rails. Intel PowerVia is a full BSPDN; TSMC's initial approach started with BPR at N2. **Design Implications** - **Cell Height Reduction**: Without power rails competing for M0/M1 routing tracks, standard cells can shrink from 6-track to 5-track height — a ~17% area reduction. - **Simplified Power Grid**: The backside has dedicated thick metals optimized purely for power (low resistance), without signal integrity constraints. - **Thermal Considerations**: Thinning the wafer changes the thermal path. The die must now dissipate heat through the backside metal stack and its bonding interface, potentially increasing thermal resistance if not carefully designed. Backside Power Delivery is **the architectural revolution that splits the chip into two domains** — signals on top, power on the bottom — ending the decades-old compromise of sharing metal layers between power and logic routing, and opening a new frontier for transistor density scaling.