power via
**Buried Power Rail (BPR) and Backside Power Delivery Network (BSPDN)** is the **advanced interconnect architecture that routes power supply (VDD/VSS) connections through the backside of the silicon substrate rather than competing with signal routing in the front-end metal stack** — freeing up front-side routing resources for signal wires, enabling significant standard cell height reduction, and lowering IR drop by providing wider, lower-resistance power rails. BPR/BSPDN is a key differentiator at 2nm and below, adopted by Intel (PowerVia), TSMC, and Samsung.
**Problem Being Solved**
- In conventional CMOS: VDD and VSS power rails occupy M1 and M2 routing layers → consume ~30–40% of available routing tracks.
- Standard cells must be tall enough to accommodate signal routes AND power rails → limits cell height reduction.
- Power rail resistance increases as M1 shrinks → IR drop worsens → performance loss.
- **BPR/BSPDN solution**: Move power rails to backside → front side entirely free for signals → smaller cells, better IR drop.
**Buried Power Rail (BPR) — Intermediate Step**
- Power rails embedded in shallow trenches below STI (below the front-end active region).
- BPR is formed during FEOL before transistors, or early in MOL.
- Connection from BPR to source/drain or standard cell power pin through a power via.
- BPR width: 10–20 nm (wider than M1 signal wires) → lower resistance.
- Intel demonstrated BPR at EUV nodes; TSMC integrating BPR at N2.
**BPR Process Integration**
```
1. Substrate: Shallow trench etch for BPR (before STI)
2. Barrier/seed deposition (TaN/W or Ru)
3. Tungsten or ruthenium fill + CMP → buried rail formed
4. STI formation above BPR
5. Normal FEOL (transistors, gate stack)
6. Power via: Etch through STI down to BPR → connect S/D to buried rail
7. Normal MOL + BEOL (signal routing only — no VDD/VSS needed in M1)
```
**Full BSPDN — Backside Power Delivery**
- More ambitious: Power network entirely on the backside of the thinned silicon.
- Process: Complete front-side processing → wafer bonding to carrier → backside grinding → backside via formation → backside metal for power distribution.
- Backside vias (BSV or through-silicon via power): Connect backside power grid to front-side S/D contacts.
- Allows very wide power rails (backside M1 = 50–200 nm width with no density restrictions).
**BSPDN Benefits**
| Metric | Conventional PDN | BSPDN |
|--------|-----------------|-------|
| Standard cell height | 6T–7T track height | 5T–5.5T (cell height reduction) |
| M1 congestion | VDD/VSS occupy 2 tracks | 0 tracks (all signal) |
| IR drop | Constrained by M1 width | 3–5× lower (wider backside rails) |
| Power density | Limited | Improved scalability |
| Routing efficiency | 60–70% usable | >90% usable |
**Intel PowerVia (2024 Demonstration)**
- Intel demonstrated standalone BSPDN test chip on Intel 4 process.
- Results: 6% frequency improvement or 30% power reduction vs. conventional PDN at same frequency.
- PowerVia integrated with RibbonFET (GAA) in Intel 18A.
- Key challenge: Backside via alignment to front-side source/drain contacts with <5 nm overlay error.
**Hybrid Bonding for Power**
- Wafer-to-wafer or die-to-wafer hybrid bonding can also implement BSPDN.
- Separate logic wafer + power delivery wafer bonded face-to-face → power delivered from dedicated power die.
- Advantage: Power die can use thicker, wider metal with separate process optimization.
**Key Technical Challenges**
- Backside via etch: Must stop precisely at the silicide contact of each source/drain → critical etch selectivity.
- Overlay: Front-to-backside alignment of BSV to S/D contacts — requires <3 nm overlay in production.
- Wafer thinning: Final Si thickness 50–100 nm → stress, warpage control during thinning.
- Thermal: Backside metals must withstand subsequent processing without damage.
BPR and BSPDN represent **the most significant BEOL architecture change in decades** — by moving power from the front of the chip to the back, this technology decouples power delivery from signal routing, enabling the standard cell height reductions and IR drop improvements that sustain CMOS scaling economics at 2nm and beyond when conventional routing approaches have reached fundamental limits.