Bspdn Trace Prior Series References in Passing

# Backside Power Delivery: Step 4 — Trace How Four Prior Series Referenced BSPDN in Passing

## 1. A Technology Mentioned, Never Explained

Before this series, backside power delivery appeared only as a forward-reference inside other
transistor-architecture series -- always as "a companion innovation" worth naming, never as
the subject of its own dedicated treatment. This step collects those mentions explicitly so
later steps can build on them without duplicating their content.

## 2. Gate-All-Around / Nanosheet Transistors (2020s), Step 12

The clearest prior mention: that step introduced BSPDN as nanosheet GAA's companion
interconnect innovation, framing it as a wafer-processing and interconnect change rather than
a device-architecture change, and noting that the two technologies arrive at the same process
nodes together because GAA's density gains make frontside congestion acute enough to justify
backside power delivery's considerable process complexity. It explicitly stated that nothing
about nanosheet GAA structurally requires BSPDN -- a valuable but separable improvement at
that point in the story.

## 3. CFET, Steps 15, 19, and 20

CFET Step 15 picked up that same thread and changed the calculus: because a CFET standard cell
has measurably less frontside routing room than a nanosheet cell at a comparable node, backside
power delivery shifts from nanosheet's optional companion to something closer to a
precondition for CFET to deliver its claimed area benefit at all. CFET's closing steps (19-20)
carried that framing forward without re-explaining BSPDN itself.

## 4. What This Series Adds That Those Mentions Did Not

Neither prior mention explained the wafer-flip and thinning process, nano-TSV formation,
buried power rail integration, IR-droop quantification, the three named commercial
implementations, or the yield and thermal tradeoffs unique to backside processing. This series
is the dedicated treatment those four prior mentions pointed toward but never delivered, and it
cross-references rather than duplicates everything summarized above.

BSPDN's Trail of Prior Mentions named as a companion innovation twice before this series existed GAA NANOSHEET STEP 12: BSPDN AS OPTIONAL COMPANION Transistor / Channel Layer Thinned Substrate / Via Field CFET STEP 15: BSPDN SHIFTS TOWARD PRECONDITION Power Trunk Return Trunk Signal Power neither prior mention explained BSPDN's own process or commercial detail this series is the dedicated treatment both pointed toward
Backside Power Delivery: Step 4 — Trace How Four Prior Series Referenced BSPDN in Passing Interconnect decoupling, nano-TSV/buried power rails, and standard-cell scaling A TECHNOLOGY MENTIONED, NE... Thinned Si Substrate <500nm Frontside Signal M0-M6 Backside Power B0-B3 Backside Power Delivery Before this series, backside power delivery appeared only as a forward-reference inside other transistor- architecture series -- always as "a companion GATE-ALL-AROUND / NANOSHEE... Thinned Si Substrate <500nm Frontside Signal M0-M6 Backside Power B0-B3 Backside Power Delivery The clearest prior mention: that step introduced BSPDN as nanosheet GAA's companion interconnect innovation, framing it as a wafer- processing and interconnect CFET, STEPS 15, 19, AND 20 Thinned Si Substrate <500nm Frontside Signal M0-M6 Backside Power B0-B3 Backside Power Delivery CFET Step 15 picked up that same thread and changed the calculus: because a CFET standard cell has measurably less frontside routing room than a nanosheet cell at a Key Semiconductor Engineering Takeaway BSPDN Step 4 uncouples power delivery from signal routing to resolve advanced node interconnect bottlenecks. Essential companion architecture deployed across 2nm and sub-2nm nodes by Intel, TSMC, and Samsung.

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